Ibex Regression Results
Date/Time run: Saturday 14 March 2026 04:39 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
9 |
10 |
90.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
1 |
15 |
6.7% |
| riscv_hint_instr_test |
10 |
10 |
100.0% |
| riscv_ebreak_test |
10 |
10 |
100.0% |
| riscv_debug_basic_test |
10 |
10 |
100.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
10 |
10 |
100.0% |
| riscv_debug_instr_test |
25 |
25 |
100.0% |
| riscv_debug_wfi_test |
10 |
10 |
100.0% |
| riscv_dret_test |
5 |
5 |
100.0% |
| riscv_debug_ebreak_test |
15 |
15 |
100.0% |
| riscv_debug_ebreakmu_test |
15 |
15 |
100.0% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
10 |
10 |
100.0% |
| riscv_debug_in_irq_test |
10 |
10 |
100.0% |
| riscv_assorted_traps_interrupts_debug_test |
5 |
10 |
50.0% |
| riscv_single_interrupt_test |
15 |
15 |
100.0% |
| riscv_multiple_interrupt_test |
10 |
10 |
100.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
15 |
15 |
100.0% |
| riscv_mem_intg_error_test |
39 |
50 |
78.0% |
| riscv_debug_single_step_test |
13 |
15 |
86.7% |
| riscv_reset_test |
15 |
15 |
100.0% |
| riscv_pc_intg_test |
13 |
15 |
86.7% |
| riscv_rf_intg_test |
100 |
100 |
100.0% |
| riscv_rf_addr_intg_test |
13 |
15 |
86.7% |
| riscv_ram_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
11 |
15 |
73.3% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
50 |
50 |
100.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
49 |
50 |
98.0% |
| riscv_pmp_full_random_test |
574 |
600 |
95.7% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
20 |
20 |
100.0% |
| riscv_epmp_rlb_test |
20 |
20 |
100.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| riscv_debug_triggers_test |
0 |
5 |
0.0% |
| Total |
1457 |
1530 |
95.2% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 90.0% |
93.8% |
88.6% |
94.8% |
90.8% |
94.5% |
100.0% |
98.7% |
Test Failure Details
riscv_rand_jump_test.18006
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.18006/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 71002011: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 71002011: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.18000
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
134: 393486: Illegal instruction (hart 0) at PC 0x80009398: 0x00000000
135: 393486: Illegal instruction (hart 0) at PC 0x80009398: 0x00000000
136: 393506: Illegal instruction (hart 0) at PC 0x80009398: 0x00000000
137: 393506: Illegal instruction (hart 0) at PC 0x80009398: 0x00000000
138: 393526: Illegal instruction (hart 0) at PC 0x80009398: 0x00000000
[E] 139: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 393556: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80009396
140:
141:
142: --- RISC-V UVM TEST FAILED ---
143:
--------------------------------------------
riscv_illegal_instr_test.18001
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
123: 158043: Illegal instruction (hart 0) at PC 0x80011758: 0xd155b03f
124: 158043: Illegal instruction (hart 0) at PC 0x80011758: 0xd155b03f
125: 158063: Illegal instruction (hart 0) at PC 0x80011758: 0xd155b03f
126: 220403: Illegal instruction (hart 0) at PC 0x80011a94: 0x00000000
127: 220423: Illegal instruction (hart 0) at PC 0x80011a94: 0x00000000
[E] 128: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 220433: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80011a92
129:
130:
131: --- RISC-V UVM TEST FAILED ---
132:
--------------------------------------------
riscv_illegal_instr_test.18002
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
173: 400940: Illegal instruction (hart 0) at PC 0x80004240: 0xee1973f3
174: 439540: Illegal instruction (hart 0) at PC 0x800043f6: 0xa1a1ecf3
175: 439560: Illegal instruction (hart 0) at PC 0x800043f6: 0xa1a1ecf3
176: 471540: Illegal instruction (hart 0) at PC 0x80004408: 0x00000000
177: 471560: Illegal instruction (hart 0) at PC 0x80004408: 0x00000000
[E] 178: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 471570: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004406
179:
180:
181: --- RISC-V UVM TEST FAILED ---
182:
--------------------------------------------
riscv_illegal_instr_test.18003
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
151: 218897: Illegal instruction (hart 0) at PC 0x80004234: 0x00000000
152: 218897: Illegal instruction (hart 0) at PC 0x80004234: 0x00000000
153: 218917: Illegal instruction (hart 0) at PC 0x80004234: 0x00000000
154: 218917: Illegal instruction (hart 0) at PC 0x80004234: 0x00000000
155: 218937: Illegal instruction (hart 0) at PC 0x80004234: 0x00000000
[E] 156: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 218967: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004232
157:
158:
159: --- RISC-V UVM TEST FAILED ---
160:
--------------------------------------------
riscv_illegal_instr_test.18004
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
335: 740707: Illegal instruction (hart 0) at PC 0x80004cd8: 0x5731ad53
336: 740727: Illegal instruction (hart 0) at PC 0x80004cd8: 0x5731ad53
337: 787247: Illegal instruction (hart 0) at PC 0x80004ea4: 0x1ed1dc0f
338: 787267: Illegal instruction (hart 0) at PC 0x80004ea4: 0x1ed1dc0f
339: xmsim: *E,ASRTST (./tb/core_ibex_tb_top.sv,191): (time 825417 NS) Assertion core_ibex_tb_top.NoAlertsTriggered has failed
[E] 340: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(191) @ 825417: reporter [ASSERT FAILED] NoAlertsTriggered
341:
342: --- RISC-V UVM TEST FAILED ---
343:
344: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 825417: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.18005
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
153: 244244: Illegal instruction (hart 0) at PC 0x80003934: 0x47d3ce73
154: 312344: Illegal instruction (hart 0) at PC 0x80003bc8: 0x0107dcbb
155: 312364: Illegal instruction (hart 0) at PC 0x80003bc8: 0x0107dcbb
156: 351964: Illegal instruction (hart 0) at PC 0x80003c44: 0x00000000
157: 351984: Illegal instruction (hart 0) at PC 0x80003c44: 0x00000000
[E] 158: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 352014: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003c42
159:
160:
161: --- RISC-V UVM TEST FAILED ---
162:
--------------------------------------------
riscv_illegal_instr_test.18006
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
203: 597281: Illegal instruction (hart 0) at PC 0x80004da6: 0x40918273
204: 626761: Illegal instruction (hart 0) at PC 0x80004e7a: 0xa180aff3
205: 626781: Illegal instruction (hart 0) at PC 0x80004e7a: 0xa180aff3
206: 658001: Illegal instruction (hart 0) at PC 0x80004fde: 0x00000000
207: 658021: Illegal instruction (hart 0) at PC 0x80004fde: 0x00000000
[E] 208: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 658051: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004fdc
209:
210:
211: --- RISC-V UVM TEST FAILED ---
212:
--------------------------------------------
riscv_illegal_instr_test.18007
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
110: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_illegal_instr_test.18007/trace_core_00000000.log
111: 66798: Illegal instruction (hart 0) at PC 0x80003710: 0xd8a9f0f3
112: 66818: Illegal instruction (hart 0) at PC 0x80003710: 0xd8a9f0f3
113: 175578: Illegal instruction (hart 0) at PC 0x80003da4: 0x00000000
114: 175598: Illegal instruction (hart 0) at PC 0x80003da4: 0x00000000
[E] 115: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 175628: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003da2
116:
117:
118: --- RISC-V UVM TEST FAILED ---
119:
--------------------------------------------
riscv_illegal_instr_test.18008
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
333: 1638655: Illegal instruction (hart 0) at PC 0x800067e0: 0x00007076
334: 1666455: Illegal instruction (hart 0) at PC 0x80006938: 0x3ce3ace7
335: 1666475: Illegal instruction (hart 0) at PC 0x80006938: 0x3ce3ace7
336: 1705075: Illegal instruction (hart 0) at PC 0x80006ab8: 0x00000000
337: 1705095: Illegal instruction (hart 0) at PC 0x80006ab8: 0x00000000
[E] 338: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1705125: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80006ab6
339:
340:
341: --- RISC-V UVM TEST FAILED ---
342:
--------------------------------------------
riscv_illegal_instr_test.18009
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
270: 909885: Illegal instruction (hart 0) at PC 0x80005496: 0x00000000
271: 909885: Illegal instruction (hart 0) at PC 0x80005496: 0x00000000
272: 909905: Illegal instruction (hart 0) at PC 0x80005496: 0x00000000
273: 909905: Illegal instruction (hart 0) at PC 0x80005496: 0x00000000
274: 909925: Illegal instruction (hart 0) at PC 0x80005496: 0x00000000
[E] 275: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 909955: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80005494
276:
277:
278: --- RISC-V UVM TEST FAILED ---
279:
--------------------------------------------
riscv_illegal_instr_test.18010
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
148: 43381: Illegal instruction (hart 0) at PC 0x8000365a: 0x00000000
149: 43381: Illegal instruction (hart 0) at PC 0x8000365a: 0x00000000
150: 43401: Illegal instruction (hart 0) at PC 0x8000365a: 0x00000000
151: 43401: Illegal instruction (hart 0) at PC 0x8000365a: 0x00000000
152: 43421: Illegal instruction (hart 0) at PC 0x8000365a: 0x00000000
[E] 153: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 43451: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80003658
154:
155:
156: --- RISC-V UVM TEST FAILED ---
157:
--------------------------------------------
riscv_illegal_instr_test.18011
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
387: 1298858: Illegal instruction (hart 0) at PC 0x80005b3c: 0x00000000
388: 1298858: Illegal instruction (hart 0) at PC 0x80005b3c: 0x00000000
389: 1298878: Illegal instruction (hart 0) at PC 0x80005b3c: 0x00000000
390: 1298878: Illegal instruction (hart 0) at PC 0x80005b3c: 0x00000000
391: 1298898: Illegal instruction (hart 0) at PC 0x80005b3c: 0x00000000
[E] 392: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1298928: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80005b3a
393:
394:
395: --- RISC-V UVM TEST FAILED ---
396:
--------------------------------------------
riscv_illegal_instr_test.18013
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
417: 2008012: Illegal instruction (hart 0) at PC 0x8000594c: 0xa1432287
418: 2076412: Illegal instruction (hart 0) at PC 0x80005bb4: 0x00000000
419: 2076432: Illegal instruction (hart 0) at PC 0x80005bb4: 0x00000000
420: 2076432: Illegal instruction (hart 0) at PC 0x80005bb4: 0x00000000
421: 2076452: Illegal instruction (hart 0) at PC 0x80005bb4: 0x00000000
[E] 422: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2076482: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002300 but the DUT didn't report one at PC 80005bb2
423:
424:
425: --- RISC-V UVM TEST FAILED ---
426:
--------------------------------------------
riscv_illegal_instr_test.18014
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
225: 1186542: Illegal instruction (hart 0) at PC 0x80008436: 0x00000000
226: 1186542: Illegal instruction (hart 0) at PC 0x80008436: 0x00000000
227: 1186562: Illegal instruction (hart 0) at PC 0x80008436: 0x00000000
228: 1186562: Illegal instruction (hart 0) at PC 0x80008436: 0x00000000
229: 1186582: Illegal instruction (hart 0) at PC 0x80008436: 0x00000000
[E] 230: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1186612: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80008434
231:
232:
233: --- RISC-V UVM TEST FAILED ---
234:
--------------------------------------------
riscv_debug_triggers_test.18000
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
193: 2159866: Illegal instruction (hart 0) at PC 0x8000556e: 0x00000010
194: 2171926: Illegal instruction (hart 0) at PC 0x80005576: 0xe1345edb
195: 2171946: Illegal instruction (hart 0) at PC 0x80005576: 0xe1345edb
196: 2207226: Illegal instruction (hart 0) at PC 0x800056d2: 0x00000000
197: 2207246: Illegal instruction (hart 0) at PC 0x800056d2: 0x00000000
[E] 198: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2207276: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800056d0
199:
200:
201: --- RISC-V UVM TEST FAILED ---
202:
--------------------------------------------
riscv_debug_triggers_test.18001
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
197: 2357783: Illegal instruction (hart 0) at PC 0x80005670: 0x02fc72bb
198: 2395763: Illegal instruction (hart 0) at PC 0x800056f6: 0x2cc671f3
199: 2395783: Illegal instruction (hart 0) at PC 0x800056f6: 0x2cc671f3
200: 2473963: Illegal instruction (hart 0) at PC 0x8000585a: 0x00000000
201: 2473983: Illegal instruction (hart 0) at PC 0x8000585a: 0x00000000
[E] 202: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2474013: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80005858
203:
204:
205: --- RISC-V UVM TEST FAILED ---
206:
--------------------------------------------
riscv_debug_triggers_test.18002
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
371: 5260900: Illegal instruction (hart 0) at PC 0x80009d32: 0x5407cb8b
372: 5316680: Illegal instruction (hart 0) at PC 0x80009e0c: 0x37287d9f
373: 5316700: Illegal instruction (hart 0) at PC 0x80009e0c: 0x37287d9f
374: 5334760: Illegal instruction (hart 0) at PC 0x80009e54: 0x00000000
375: 5334780: Illegal instruction (hart 0) at PC 0x80009e54: 0x00000000
[E] 376: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 5334810: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80009e52
377:
378:
379: --- RISC-V UVM TEST FAILED ---
380:
--------------------------------------------
riscv_debug_triggers_test.18003
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
169: 1825377: Illegal instruction (hart 0) at PC 0x800048c8: 0x00000000
170: 1825377: Illegal instruction (hart 0) at PC 0x800048c8: 0x00000000
171: 1825397: Illegal instruction (hart 0) at PC 0x800048c8: 0x00000000
172: 1825397: Illegal instruction (hart 0) at PC 0x800048c8: 0x00000000
173: 1825417: Illegal instruction (hart 0) at PC 0x800048c8: 0x00000000
[E] 174: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1825447: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800048c6
175:
176:
177: --- RISC-V UVM TEST FAILED ---
178:
--------------------------------------------
riscv_debug_triggers_test.18004
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
257: 2803487: Illegal instruction (hart 0) at PC 0x80005ee0: 0x00000000
258: 2803487: Illegal instruction (hart 0) at PC 0x80005ee0: 0x00000000
259: 2803507: Illegal instruction (hart 0) at PC 0x80005ee0: 0x00000000
260: 2803507: Illegal instruction (hart 0) at PC 0x80005ee0: 0x00000000
261: 2803527: Illegal instruction (hart 0) at PC 0x80005ee0: 0x00000000
[E] 262: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2803557: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80005ede
263:
264:
265: --- RISC-V UVM TEST FAILED ---
266:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.18000
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 232476: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/5
120: 259246: Illegal instruction (hart 0) at PC 0x8000c2d6: 0x00002108
121: 259266: Illegal instruction (hart 0) at PC 0x8000c2d6: 0x00002108
122: 315026: Illegal instruction (hart 0) at PC 0x8000658e: 0x00000000
123: 315046: Illegal instruction (hart 0) at PC 0x8000658e: 0x00000000
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 315076: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000658c
125:
126:
127: --- RISC-V UVM TEST FAILED ---
128:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.18001
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
129: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 269873: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/9
130: 284763: Illegal instruction (hart 0) at PC 0x8000ce36: 0x00008d64
131: 284783: Illegal instruction (hart 0) at PC 0x8000ce36: 0x00008d64
132: 369403: Illegal instruction (hart 0) at PC 0x800069de: 0x30008253
133: 369423: Illegal instruction (hart 0) at PC 0x800069de: 0x30008253
[E] 134: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 383273: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000cd9e
135:
136:
137: --- RISC-V UVM TEST FAILED ---
138:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.18006
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
170: 1440801: Illegal instruction (hart 0) at PC 0x0000002c: 0x00000000
171: 1453621: Illegal instruction (hart 0) at PC 0x00000030: 0x00000000
172: 1453641: Illegal instruction (hart 0) at PC 0x00000030: 0x00000000
173: 1543141: Illegal instruction (hart 0) at PC 0x8000c8ba: 0x81b3001b
174: 1543161: Illegal instruction (hart 0) at PC 0x8000c8ba: 0x81b3001b
[E] 175: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1545151: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000cdbc
176:
177:
178: --- RISC-V UVM TEST FAILED ---
179:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.18007
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(75) @ 34248: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Number of stimulus iterations = 7
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 34248: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 0/7
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 34248: uvm_test_top.env.irq_agent.sequencer@@irq_new_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_new_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
115: 74798: Illegal instruction (hart 0) at PC 0x8000387a: 0x00000000
116: 74818: Illegal instruction (hart 0) at PC 0x8000387a: 0x00000000
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 74848: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80003878
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.18008
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
128: 309055: Illegal instruction (hart 0) at PC 0x8000be04: 0x5159b373
129: 425955: Illegal instruction (hart 0) at PC 0x8000be04: 0x5159b373
130: 425975: Illegal instruction (hart 0) at PC 0x8000be04: 0x5159b373
131: 482315: Illegal instruction (hart 0) at PC 0x8000be04: 0x5159b373
132: 482335: Illegal instruction (hart 0) at PC 0x8000be04: 0x5159b373
[E] 133: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 483305: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80002850 , but the ISS retired: 80003ae8
134:
135:
136: --- RISC-V UVM TEST FAILED ---
137:
--------------------------------------------
riscv_mem_intg_error_test.18006
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.18006/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 18091: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 18091: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 40031: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 83991: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 92411: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x7 DUT: 8001dd5a expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.18009
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.18009/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 12335: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12335: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 12335: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 53075: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x19 DUT: 8001347d expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.18015
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 12089: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12089: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 12089: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 61729: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 155269: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 189849: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 80018250 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.18016
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 14866: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14866: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 99746: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 162886: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 182786: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 197486: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x30 DUT: 80023290 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.18023
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 22038: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 22038: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 22038: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 74738: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 152178: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 203638: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x16 DUT: 80012524 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.18027
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 13598: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
122: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 60978: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
123: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 126518: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
124: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 188998: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
125: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 257698: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 126: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 283918: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x19 DUT: 80013843 expected: 0
127:
128:
129: --- RISC-V UVM TEST FAILED ---
130:
--------------------------------------------
riscv_mem_intg_error_test.18029
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.18029/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 60505: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 60505: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 83385: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 125905: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 8001f819 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.18035
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.18035/trace_core_00000000.log
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 14240: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14240: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 14240: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 58080: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x2 DUT: 80028e40 expected: 0
123:
124:
125: --- RISC-V UVM TEST FAILED ---
126:
--------------------------------------------
riscv_mem_intg_error_test.18037
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 17174: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 68694: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 131174: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 181454: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 208274: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 236174: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x4 DUT: 80013317 expected: 0
121:
122:
123: --- RISC-V UVM TEST FAILED ---
124:
--------------------------------------------
riscv_mem_intg_error_test.18044
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 16338: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 70178: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 111018: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 186938: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 240678: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 274898: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x10 DUT: 80013c8f expected: 0
121:
122:
123: --- RISC-V UVM TEST FAILED ---
124:
--------------------------------------------
riscv_mem_intg_error_test.18045
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.18045/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 15735: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 15735: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 15735: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 71095: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x16 DUT: 80013be0 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_debug_single_step_test.18005
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
187: 5000744: Illegal instruction (hart 0) at PC 0x40000166: 0x00000000
188: 5013684: Illegal instruction (hart 0) at PC 0x4000016a: 0x00000000
189: 5013704: Illegal instruction (hart 0) at PC 0x4000016a: 0x00000000
190: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 5018254: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
191: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 5019754: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 192: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 5437914: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x11 DUT: 0 expected: 7e00
193:
194:
195: --- RISC-V UVM TEST FAILED ---
196:
--------------------------------------------
riscv_debug_single_step_test.18013
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 72922: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
116: 622512: Illegal instruction (hart 0) at PC 0x8000311a: 0x7b200073
117: 622532: Illegal instruction (hart 0) at PC 0x8000311a: 0x7b200073
118: 772952: Illegal instruction (hart 0) at PC 0x80003172: 0x7b200073
119: 772972: Illegal instruction (hart 0) at PC 0x80003172: 0x7b200073
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 813882: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002300 but the DUT didn't report one at PC 8000abb4
121:
122:
123: --- RISC-V UVM TEST FAILED ---
124:
--------------------------------------------
riscv_pc_intg_test.18006
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.18006/trace_core_00000000.log not found
riscv_pc_intg_test.18007
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.18007/trace_core_00000000.log not found
riscv_rf_addr_intg_test.18005
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rf_addr_intg_test.18005/trace_core_00000000.log
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(266) @ 88224: uvm_test_top [uvm_test_top] Reading value of core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_a_i
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(268) @ 88224: uvm_test_top [uvm_test_top] Read 00000009
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(278) @ 88224: uvm_test_top [uvm_test_top] Forcing core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_a_i to value 'h8
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 88224: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(294) @ 88225: reporter [uvm_test_top] Check failed (|ecc_err) ECC alert did not fire!
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 88225: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_rf_addr_intg_test.18011
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rf_addr_intg_test.18011/trace_core_00000000.log
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(266) @ 28578: uvm_test_top [uvm_test_top] Reading value of core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_b_i
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(268) @ 28578: uvm_test_top [uvm_test_top] Read 0000000c
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(278) @ 28578: uvm_test_top [uvm_test_top] Forcing core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_b_i to value 'h4
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 28578: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(294) @ 28579: reporter [uvm_test_top] Check failed (|ecc_err) ECC alert did not fire!
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 28579: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.18001
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 37363: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 37363: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 37363: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700099810370073004f
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 37363: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700099810330073004f
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 37363: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 37383: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37383: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.18002
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 24860: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 24860: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 24860: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d301b98107b007301b5
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 24860: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d301b98107b007301a5
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 24860: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 24880: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 24880: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.18006
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 22101: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 22101: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 22101: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037881b9810400073007a
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 22101: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037881b9810400873007a
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 22101: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 22121: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 22121: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.18007
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 31638: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 31638: uvm_test_top [uvm_test_top] Corrupting data way 0
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 31638: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012801b98103a00730197
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 31638: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012801b98003a00730197
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 31638: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 31658: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
123:
124: --- RISC-V UVM TEST FAILED ---
125:
126: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 31658: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.18035
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.18035/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 12002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 12002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.18010
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(204) @ 2011: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18010/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 186271: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data e10000 but data 0 was expected with byte mask 4
118: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003f06
119:
120:
121: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18015
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18015/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 108309: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 95000000 but data 0 was expected with byte mask 8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18048
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2046: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2046: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2046: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2046: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18048/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 753086: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data c0000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000d75c
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18051
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18051/trace_core_00000000.log
117: 25780: Illegal instruction (hart 0) at PC 0x8000fd2a: 0x3a096073
118: 25800: Illegal instruction (hart 0) at PC 0x8000fd2a: 0x3a096073
119: 51120: Illegal instruction (hart 0) at PC 0x8000fd3c: 0x3b0c1073
120: 51140: Illegal instruction (hart 0) at PC 0x8000fd3c: 0x3b0c1073
[E] 121: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 108530: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x8 DUT: 0 expected: ffffffff
122:
123:
124: --- RISC-V UVM TEST FAILED ---
125:
--------------------------------------------
riscv_pmp_full_random_test.18059
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
185: 4740262: Illegal instruction (hart 0) at PC 0x80003ab6: 0x3b071073
186: 4756762: Illegal instruction (hart 0) at PC 0x80003ac6: 0x3a0a6073
187: 4756782: Illegal instruction (hart 0) at PC 0x80003ac6: 0x3a0a6073
188: 4768782: Illegal instruction (hart 0) at PC 0x80003ad6: 0x3b071073
189: 4768802: Illegal instruction (hart 0) at PC 0x80003ad6: 0x3b071073
[E] 190: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 4787532: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data f5000000 but data 0 was expected with byte mask 8
191: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003adc
192:
193:
194: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18061
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18061/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 94626: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 35000000 but data 0 was expected with byte mask 8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18089
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18089/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 27158: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 33000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 800033c0
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18160
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2023: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2023: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2023: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2023: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18160/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 420283: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800051fa
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18169
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2021: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18169/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 66721: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 2f0000 but data 0 was expected with byte mask 4
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 800034b8
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18181
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2010: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18181/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2913790: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data e10000 but data 0 was expected with byte mask 4
113: Synchronous trap was expected at ISS PC: 80001f00 but the DUT didn't report one at PC 80003376
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18190
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18190/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 39529: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8001b1c8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18202
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
213: 531908: Illegal instruction (hart 0) at PC 0x800040dc: 0x3a09e073
214: 531908: Illegal instruction (hart 0) at PC 0x800040dc: 0x3a09e073
215: 531928: Illegal instruction (hart 0) at PC 0x800040dc: 0x3a09e073
216: 566148: Illegal instruction (hart 0) at PC 0x800040ee: 0x3b091073
217: 566168: Illegal instruction (hart 0) at PC 0x800040ee: 0x3b091073
[E] 218: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 595298: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 48000000 but data 0 was expected with byte mask 8
219: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80004206
220:
221:
222: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18209
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2023: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2023: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2023: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2023: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18209/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 50703: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ab000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8001bb04
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18310
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18310/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 263894: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 31000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80009102
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18342
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18342/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 36414: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800035ba
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18426
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18426/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 159638: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 69000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003ec8
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18439
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18439/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 50477: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 88000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 800031c4
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18448
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
247: 609206: Illegal instruction (hart 0) at PC 0x80004864: 0x3b0e9073
248: 626206: Illegal instruction (hart 0) at PC 0x80004868: 0x3a0ae073
249: 626226: Illegal instruction (hart 0) at PC 0x80004868: 0x3a0ae073
250: 644026: Illegal instruction (hart 0) at PC 0x8000487a: 0x3b0e9073
251: 644046: Illegal instruction (hart 0) at PC 0x8000487a: 0x3b0e9073
[E] 252: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 659376: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 62000000 but data 0 was expected with byte mask 8
253: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004880
254:
255:
256: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18449
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18449/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 993833: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80006340
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18450
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2030: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2030: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2030: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2030: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18450/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 191990: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 5a000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003d54
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18452
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18452/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 289336: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 96000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80016f92
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18456
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18456/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 221144: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data f9000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000404e
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18464
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18464/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 996146: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ab000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000c922
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.18541
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18541/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 332905: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data f000000 but data 0 was expected with byte mask 8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18586
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18586/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 782665: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 80004ed6
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.18593
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.18593/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 108509: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003c38
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------