Ibex Regression Results
Date/Time run: Friday 10 May 2024 04:07 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
9 |
10 |
90.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
15 |
15 |
100.0% |
| riscv_hint_instr_test |
8 |
10 |
80.0% |
| riscv_ebreak_test |
8 |
10 |
80.0% |
| riscv_debug_basic_test |
10 |
10 |
100.0% |
| riscv_debug_triggers_test |
5 |
5 |
100.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
10 |
10 |
100.0% |
| riscv_debug_instr_test |
23 |
25 |
92.0% |
| riscv_debug_wfi_test |
9 |
10 |
90.0% |
| riscv_dret_test |
3 |
5 |
60.0% |
| riscv_debug_ebreak_test |
13 |
15 |
86.7% |
| riscv_debug_ebreakmu_test |
11 |
15 |
73.3% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
8 |
10 |
80.0% |
| riscv_debug_in_irq_test |
7 |
10 |
70.0% |
| riscv_single_interrupt_test |
14 |
15 |
93.3% |
| riscv_multiple_interrupt_test |
9 |
10 |
90.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
14 |
15 |
93.3% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
15 |
15 |
100.0% |
| riscv_mem_intg_error_test |
44 |
50 |
88.0% |
| riscv_debug_single_step_test |
15 |
15 |
100.0% |
| riscv_reset_test |
14 |
15 |
93.3% |
| riscv_pc_intg_test |
12 |
15 |
80.0% |
| riscv_rf_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
15 |
15 |
100.0% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
46 |
50 |
92.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
47 |
50 |
94.0% |
| riscv_pmp_full_random_test |
539 |
600 |
89.8% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
18 |
20 |
90.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
18 |
20 |
90.0% |
| riscv_epmp_rlb_test |
18 |
20 |
90.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| riscv_assorted_traps_interrupts_debug_test |
0 |
10 |
0.0% |
| Total |
1297 |
1415 |
91.7% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 93.6% |
95.9% |
90.6% |
95.9% |
90.5% |
97.2% |
100.0% |
98.1% |
Test Failure Details
riscv_rand_jump_test.3875
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.3875/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 40002022: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 40002022: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_hint_instr_test.3875
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_hint_instr_test.3875/trace_core_00000000.log not found
riscv_hint_instr_test.3876
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_hint_instr_test.3876/trace_core_00000000.log not found
riscv_ebreak_test.3867
----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_ebreak_test.3867/trace_core_00000000.log not found
riscv_ebreak_test.3868
----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_ebreak_test.3868/trace_core_00000000.log not found
riscv_debug_instr_test.3881
---------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
987: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36761970: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
988: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36861050: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
989: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36862530: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
990: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36942490: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
991: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36943990: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 992: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
993:
994: --- RISC-V UVM TEST FAILED ---
995:
996: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_instr_test.3890
---------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
999: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 34731796: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1000: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 34875096: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1001: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 34876596: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1002: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 34938596: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1003: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 34940096: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1004: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 35002016: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1005:
1006: --- RISC-V UVM TEST FAILED ---
1007:
1008: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 35002016: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_wfi_test.3872
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1221: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37703632: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1222: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 37747212: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1223: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37748712: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1224: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 37797632: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1225: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37799132: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1226: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 38002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1227:
1228: --- RISC-V UVM TEST FAILED ---
1229:
1230: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 38002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.3869
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
130: 54698: Illegal instruction (hart 0) at PC 0x80003684: 0x7b200073
131: 54698: Illegal instruction (hart 0) at PC 0x80003684: 0x7b200073
132: 54718: Illegal instruction (hart 0) at PC 0x80003684: 0x7b200073
133: 54738: Illegal instruction (hart 0) at PC 0x80003684: 0x7b200073
134: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 68928: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 135: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(843) @ 75948: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
136:
137: --- RISC-V UVM TEST FAILED ---
138:
139: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 75948: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.3870
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.3870/trace_core_00000000.log
108: 75235: Illegal instruction (hart 0) at PC 0x80003884: 0x7b200073
109: 75275: Illegal instruction (hart 0) at PC 0x80003884: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 87685: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(843) @ 123405: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 123405: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreak_test.3872
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1819: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36890532: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1820: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36930392: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1821: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36931892: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1822: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36968952: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1823: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36970452: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1824: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1825:
1826: --- RISC-V UVM TEST FAILED ---
1827:
1828: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreak_test.3877
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1879: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36918469: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1880: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36953069: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1881: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36954569: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1882: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36987929: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1883: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36989449: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1884: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1885:
1886: --- RISC-V UVM TEST FAILED ---
1887:
1888: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.3872
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.3872/trace_core_00000000.log
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 44912: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 46412: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.3876
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.3876/trace_core_00000000.log
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 38272: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 39772: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.3877
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.3877/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1551) @ 28669: uvm_test_top [uvm_test_top] EBreak seen whilst doing initial debug initialization, KNOWN FAILURE SEE https://github.com/lowRISC/ibex/issues/1313
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 28669: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.3881
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.3881/trace_core_00000000.log
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 28130: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 29650: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_irq_in_debug_mode_test.3872
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
5227: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36983762: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Exiting sequence
5228: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 36983792: uvm_test_top [uvm_test_top] irq: 0x7ec0880
5229: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 36983792: uvm_test_top [uvm_test_top] irq_id: 0x13
5230: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36985752: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
5231: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36985772: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 5232: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
5233:
5234: --- RISC-V UVM TEST FAILED ---
5235:
5236: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_irq_in_debug_mode_test.3876
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4163: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35973862: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Exiting sequence
4164: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 35973892: uvm_test_top [uvm_test_top] irq: 0xd1cb0008
4165: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 35973892: uvm_test_top [uvm_test_top] irq_id: 0x1f
4166: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 35975852: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
4167: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35975862: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 4168: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4169:
4170: --- RISC-V UVM TEST FAILED ---
4171:
4172: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_in_irq_test.3872
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
3961: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 36943852: uvm_test_top [uvm_test_top] mcause: 0x8000001f
3962: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36944712: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
3963: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36946212: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
3964: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36992772: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
3965: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36992782: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 3966: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
3967:
3968: --- RISC-V UVM TEST FAILED ---
3969:
3970: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_in_irq_test.3875
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_in_irq_test.3875/trace_core_00000000.log not found
riscv_debug_in_irq_test.3876
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_in_irq_test.3876/trace_core_00000000.log not found
riscv_assorted_traps_interrupts_debug_test.3867
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
755: 8431924: Illegal instruction (hart 0) at PC 0x00000418: 0x00010413
756: 8448424: Illegal instruction (hart 0) at PC 0x0000041c: 0x00010413
757: 8448464: Illegal instruction (hart 0) at PC 0x0000041c: 0x00010413
758: 8478104: Illegal instruction (hart 0) at PC 0x00000420: 0x00010413
759: 8478144: Illegal instruction (hart 0) at PC 0x00000420: 0x00010413
[E] 760: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 8503194: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x13 DUT: 2000000 expected: 80000
761:
762:
763: --- RISC-V UVM TEST FAILED ---
764:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3868
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1608: 31034921: Illegal instruction (hart 0) at PC 0x13f5e2c2: 0x00010413
1609: 31071041: Illegal instruction (hart 0) at PC 0x13f5e2c6: 0x00010413
1610: 31071081: Illegal instruction (hart 0) at PC 0x13f5e2c6: 0x00010413
1611: 31087481: Illegal instruction (hart 0) at PC 0x13f5e2ca: 0x00010413
1612: 31087521: Illegal instruction (hart 0) at PC 0x13f5e2ca: 0x00010413
[E] 1613: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 31146251: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x21 DUT: 0 expected: 80
1614:
1615:
1616: --- RISC-V UVM TEST FAILED ---
1617:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3869
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
280: 3841718: Illegal instruction (hart 0) at PC 0x000140d0: 0x00010413
281: 3841758: Illegal instruction (hart 0) at PC 0x000140d0: 0x00010413
282: 3873358: Illegal instruction (hart 0) at PC 0x000140d4: 0x00010413
283: 3873398: Illegal instruction (hart 0) at PC 0x000140d4: 0x00010413
284: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 3899968 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 285: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 3899968: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
286:
287: --- RISC-V UVM TEST FAILED ---
288:
289: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 3899968: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3870
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
130872: 51000395: Illegal instruction (hart 0) at PC 0x80000004: 0x800036bc
130873: 51001615: Illegal instruction (hart 0) at PC 0x80000004: 0x800036bc
130874: 51001655: Illegal instruction (hart 0) at PC 0x80000004: 0x800036bc
130875: 51001795: Illegal instruction (hart 0) at PC 0x80000004: 0x800036bc
130876: 51001835: Illegal instruction (hart 0) at PC 0x80000004: 0x800036bc
[E] 130877: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 51002025: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
130878:
130879: --- RISC-V UVM TEST FAILED ---
130880:
130881: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 51002025: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3871
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1318: 21372505: Illegal instruction (hart 0) at PC 0x28af1f30: 0x00010413
1319: 21444465: Illegal instruction (hart 0) at PC 0x28af1f34: 0x00010413
1320: 21444505: Illegal instruction (hart 0) at PC 0x28af1f34: 0x00010413
1321: 21464465: Illegal instruction (hart 0) at PC 0x28af1f38: 0x00010413
1322: 21464505: Illegal instruction (hart 0) at PC 0x28af1f38: 0x00010413
[E] 1323: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 21512575: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x27 DUT: 8 expected: 0
1324:
1325:
1326: --- RISC-V UVM TEST FAILED ---
1327:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3872
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1920: 32309122: Illegal instruction (hart 0) at PC 0x00ac7b20: 0x00010413
1921: 32329322: Illegal instruction (hart 0) at PC 0x00ac7b24: 0x00010413
1922: 32329362: Illegal instruction (hart 0) at PC 0x00ac7b24: 0x00010413
1923: 32371822: Illegal instruction (hart 0) at PC 0x00ac7b28: 0x00010413
1924: 32371862: Illegal instruction (hart 0) at PC 0x00ac7b28: 0x00010413
[E] 1925: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 32441672: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 0 expected: 800000
1926:
1927:
1928: --- RISC-V UVM TEST FAILED ---
1929:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3873
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
121: 243359: Illegal instruction (hart 0) at PC 0x8000c0f2: 0x05760187
122: 243399: Illegal instruction (hart 0) at PC 0x8000c0f2: 0x05760187
123: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 247989: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/8
124: 277959: Illegal instruction (hart 0) at PC 0x8000c0f2: 0x05760187
125: 277999: Illegal instruction (hart 0) at PC 0x8000c0f2: 0x05760187
[E] 126: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 337209: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x13 DUT: 0 expected: 8
127:
128:
129: --- RISC-V UVM TEST FAILED ---
130:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3874
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
910: 15767575: Illegal instruction (hart 0) at PC 0xc93f1b8c: 0x00010413
911: 15790775: Illegal instruction (hart 0) at PC 0xc93f1b90: 0x00010413
912: 15790815: Illegal instruction (hart 0) at PC 0xc93f1b90: 0x00010413
913: 15833135: Illegal instruction (hart 0) at PC 0xc93f1b94: 0x00010413
914: 15833175: Illegal instruction (hart 0) at PC 0xc93f1b94: 0x00010413
[E] 915: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 15885845: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x5 DUT: 0 expected: 40000
916:
917:
918: --- RISC-V UVM TEST FAILED ---
919:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3875
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
471: 6808312: Illegal instruction (hart 0) at PC 0x024aff0e: 0x00010413
472: 6822992: Illegal instruction (hart 0) at PC 0x024aff12: 0x00010413
473: 6823032: Illegal instruction (hart 0) at PC 0x024aff12: 0x00010413
474: 6836152: Illegal instruction (hart 0) at PC 0x024aff16: 0x00010413
475: 6836192: Illegal instruction (hart 0) at PC 0x024aff16: 0x00010413
[E] 476: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 6871282: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x25 DUT: 10000000 expected: 1000000
477:
478:
479: --- RISC-V UVM TEST FAILED ---
480:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3876
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
176: 969362: Illegal instruction (hart 0) at PC 0x8fffffde: 0x00010413
177: 981722: Illegal instruction (hart 0) at PC 0x8fffffe2: 0x00010413
178: 981762: Illegal instruction (hart 0) at PC 0x8fffffe2: 0x00010413
179: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 1084432: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 5/6
180: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 1286712: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 6/6
[E] 181: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
182:
183: --- RISC-V UVM TEST FAILED ---
184:
185: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_single_interrupt_test.3867
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
10991: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 35981994: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Starting sequence...
10992: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35982014: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Exiting sequence
10993: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 35982034: uvm_test_top [uvm_test_top] irq: 0x40000
10994: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 35982034: uvm_test_top [uvm_test_top] irq_id: 0x12
10995: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 35994774: uvm_test_top [uvm_test_top] mcause: 0x80000012
[E] 10996: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002014: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
10997:
10998: --- RISC-V UVM TEST FAILED ---
10999:
11000: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002014: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_multiple_interrupt_test.3872
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
8575: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 36975612: uvm_test_top [uvm_test_top] irq: 0x3a440808
8576: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 36975612: uvm_test_top [uvm_test_top] irq_id: 0x16
8577: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 36985132: uvm_test_top [uvm_test_top] mcause: 0x80000016
8578: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36990592: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
8579: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36990602: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 8580: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
8581:
8582: --- RISC-V UVM TEST FAILED ---
8583:
8584: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_interrupt_wfi_test.3881
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
10162: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 42995670: uvm_test_top [uvm_test_top] irq_id: 0xb
10163: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 42995670: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
10164: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 42995680: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
10165: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 42995710: uvm_test_top [uvm_test_top] irq: 0x0
10166: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 42995710: uvm_test_top [uvm_test_top] irq_id: 0xb
[E] 10167: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 43002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
10168:
10169: --- RISC-V UVM TEST FAILED ---
10170:
10171: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 43002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_mem_intg_error_test.3873
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3873/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 15649: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 15649: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 15649: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 111949: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 167689: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x28 DUT: 80012936 expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.3881
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 13170: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13170: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 13170: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 52890: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 69590: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 74090: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x22 DUT: 80020730 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.3892
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3892/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 13642: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13642: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 67382: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 103482: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x20 DUT: 80012e89 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.3897
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3897/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 19980: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 19980: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 54440: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 93840: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x14 DUT: 80013ffd expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.3904
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 12952: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12952: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 12952: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 94592: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 126732: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 182712: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x6 DUT: 80012696 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.3907
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 14236: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14236: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 48536: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 115576: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 143056: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 162496: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x7 DUT: 800234fb expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_reset_test.3881
---------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
225: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 29928470: uvm_test_top [uvm_test_top] Reset now inactive
226: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 30016935: uvm_test_top [uvm_test_top] Reset now active
227: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 30018930: uvm_test_top [uvm_test_top] Reset now inactive
228: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 30304650: uvm_test_top [uvm_test_top] Reset now active
229: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 30306650: uvm_test_top [uvm_test_top] Reset now inactive
[E] 230: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 34002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
231:
232: --- RISC-V UVM TEST FAILED ---
233:
234: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 34002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pc_intg_test.3867
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3867/trace_core_00000000.log not found
riscv_pc_intg_test.3876
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3876/trace_core_00000000.log not found
riscv_pc_intg_test.3879
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3879/trace_core_00000000.log not found
riscv_pmp_basic_test.3876
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.3876/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_basic_test.3885
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.3885/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002018: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002018: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_basic_test.3890
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.3890/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002016: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002016: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_basic_test.3901
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2041: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2041: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2041: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2041: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.3901/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002041: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002041: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3880
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3880/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3890
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3890/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002016: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002016: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3903
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3903/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002015: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002015: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.3867
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3867/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2118454: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80017756
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.3885
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3885/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 209478: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 60000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3902
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3902/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 507718: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 7c000000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002300 but the DUT didn't report one at PC 80002382
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3922
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3922/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 523389: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 40000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3933
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2021: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3933/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 831241: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003dec
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.3935
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3935/trace_core_00000000.log
112: 20905: Illegal instruction (hart 0) at PC 0x800034ec: 0x3a0b6073
113: 20945: Illegal instruction (hart 0) at PC 0x800034ec: 0x3a0b6073
114: 55185: Illegal instruction (hart 0) at PC 0x800034fc: 0x3b041073
115: 55225: Illegal instruction (hart 0) at PC 0x800034fc: 0x3b041073
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 467135: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80036ce0 was expected
117: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
118:
119:
120: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3947
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3947/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1886797: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address cc04b50 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3949
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3949/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 68991: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 80000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3952
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3952/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1404595: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 13800000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3960
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
119: 2216453: Illegal instruction (hart 0) at PC 0x8001a524: 0x3a09e073
120: 2216473: Illegal instruction (hart 0) at PC 0x8001a524: 0x3a09e073
121: 2216493: Illegal instruction (hart 0) at PC 0x8001a524: 0x3a09e073
122: 2245513: Illegal instruction (hart 0) at PC 0x8001a536: 0x3b031073
123: 2245553: Illegal instruction (hart 0) at PC 0x8001a536: 0x3b031073
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2262383: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 48000000 but store at address 80035ce0 was expected
125: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
126:
127:
128: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3967
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: 1164618: Illegal instruction (hart 0) at PC 0x800035d2: 0x3a09e073
114: 1203418: Illegal instruction (hart 0) at PC 0x800035d2: 0x3a09e073
115: 1203458: Illegal instruction (hart 0) at PC 0x800035d2: 0x3a09e073
116: 1224518: Illegal instruction (hart 0) at PC 0x800035e4: 0x3b081073
117: 1224558: Illegal instruction (hart 0) at PC 0x800035e4: 0x3b081073
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1246828: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80036ce0 was expected
119: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
120:
121:
122: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3993
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3993/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 28993: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 1ac7640 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.3999
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3999/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 48308: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 800034aa
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4003
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4003/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1177569: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 45e00000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4010
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4010/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 54120: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80003382
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4012
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4012/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 647847: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80004a46
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4013
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4013/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1086744: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 68461c00 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4014
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2021: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4014/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1214101: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 386af600 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4015
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2038: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2038: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2038: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2038: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4015/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 193438: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address c68e000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4020
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4020/trace_core_00000000.log
112: 31606: Illegal instruction (hart 0) at PC 0x800034bc: 0x3a08e073
113: 31646: Illegal instruction (hart 0) at PC 0x800034bc: 0x3a08e073
114: 59906: Illegal instruction (hart 0) at PC 0x800034ce: 0x3b0e9073
115: 59946: Illegal instruction (hart 0) at PC 0x800034ce: 0x3b0e9073
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2026356: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 3c000000 but store at address 80036ce0 was expected
117: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
118:
119:
120: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4032
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4032/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1467918: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 5e261800 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4037
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4037/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2268516: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 78900000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4042
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4042/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 37494: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4043
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4043/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 31691: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80008e26
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4049
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2045: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2045: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2045: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2045: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4049/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2328365: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 781f8000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4051
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4051/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 64472: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 307a0000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4053
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4053/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1529326: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 5b200000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4062
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4062/trace_core_00000000.log
112: 108354: Illegal instruction (hart 0) at PC 0x80002f54: 0x3a0a6073
113: 108394: Illegal instruction (hart 0) at PC 0x80002f54: 0x3a0a6073
114: 129914: Illegal instruction (hart 0) at PC 0x80002f64: 0x3b079073
115: 129954: Illegal instruction (hart 0) at PC 0x80002f64: 0x3b079073
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 914944: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 8000301c
117:
118:
119: --- RISC-V UVM TEST FAILED ---
120:
--------------------------------------------
riscv_pmp_full_random_test.4064
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4064/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 27138: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 3a564700 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4074
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4074/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 43374: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 6f80a200 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 80002282
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4100
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4100/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1986259: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000348a
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4101
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4101/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 848629: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 800034a2
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4105
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4105/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 994017: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 69a64480 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4113
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4113/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 384798: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80004a72
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4115
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4115/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 839032: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address e4c0000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4120
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
153: 31740: Illegal instruction (hart 0) at PC 0x80003436: 0x3a086073
154: 31760: Illegal instruction (hart 0) at PC 0x80003436: 0x3a086073
155: 31780: Illegal instruction (hart 0) at PC 0x80003436: 0x3a086073
156: 62280: Illegal instruction (hart 0) at PC 0x80003448: 0x3b0d9073
157: 62320: Illegal instruction (hart 0) at PC 0x80003448: 0x3b0d9073
[E] 158: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 96190: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 26afd3e0 but store at address 80035ce0 was expected
159: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
160:
161:
162: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4130
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4130/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1083138: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 8e3b8000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4154
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4154/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 33117: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800034ea
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4155
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4155/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 93967: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address f6f2240 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4175
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4175/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1356978: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 310b8a0 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4181
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: 152222: Illegal instruction (hart 0) at PC 0x80018dd2: 0x3a09e073
114: 152242: Illegal instruction (hart 0) at PC 0x80018dd2: 0x3a09e073
115: 152242: Illegal instruction (hart 0) at PC 0x80018dd2: 0x3a09e073
116: 152262: Illegal instruction (hart 0) at PC 0x80018dd2: 0x3a09e073
117: 152282: Illegal instruction (hart 0) at PC 0x80018dd2: 0x3a09e073
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 152492: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 5ec0400 but store at address 80036ce0 was expected
119: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
120:
121:
122: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4190
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4190/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 50831: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 658fab40 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4191
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4191/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1726828: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 37212000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4212
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4212/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2405756: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 8000339a
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.4218
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2010: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4218/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 33250: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 2c7b0000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80001f00 but the DUT didn't report one at PC 80001f82
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4219
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4219/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 39447: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 7e00000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4221
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
119: 1109324: Illegal instruction (hart 0) at PC 0x80003444: 0x3a0ae073
120: 1109344: Illegal instruction (hart 0) at PC 0x80003444: 0x3a0ae073
121: 1109364: Illegal instruction (hart 0) at PC 0x80003444: 0x3a0ae073
122: 1130484: Illegal instruction (hart 0) at PC 0x80003456: 0x3b029073
123: 1130524: Illegal instruction (hart 0) at PC 0x80003456: 0x3b029073
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1261534: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 25fc4000 but store at address 80035ce0 was expected
125: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
126:
127:
128: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4224
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4224/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 101825: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address c3eb180 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4232
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
177: 502436: Illegal instruction (hart 0) at PC 0x80003d70: 0x3a0ae073
178: 502456: Illegal instruction (hart 0) at PC 0x80003d70: 0x3a0ae073
179: 502456: Illegal instruction (hart 0) at PC 0x80003d70: 0x3a0ae073
180: 502476: Illegal instruction (hart 0) at PC 0x80003d70: 0x3a0ae073
181: 502496: Illegal instruction (hart 0) at PC 0x80003d70: 0x3a0ae073
[E] 182: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 502706: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 5acc0000 but store at address 80035ce0 was expected
183: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
184:
185:
186: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4234
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4234/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 21900: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 6d184200 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4238
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
135: 767691: Illegal instruction (hart 0) at PC 0x8000347a: 0x3a08e073
136: 767711: Illegal instruction (hart 0) at PC 0x8000347a: 0x3a08e073
137: 767731: Illegal instruction (hart 0) at PC 0x8000347a: 0x3a08e073
138: 792171: Illegal instruction (hart 0) at PC 0x8000348c: 0x3b0d1073
139: 792211: Illegal instruction (hart 0) at PC 0x8000348c: 0x3b0d1073
[E] 140: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 826741: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 66ac0000 but store at address 80035ce0 was expected
141: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
142:
143:
144: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4254
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4254/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 473671: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 40000000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4259
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
129: 2460959: Illegal instruction (hart 0) at PC 0x80003392: 0x3a0b6073
130: 2511559: Illegal instruction (hart 0) at PC 0x80003392: 0x3a0b6073
131: 2511599: Illegal instruction (hart 0) at PC 0x80003392: 0x3a0b6073
132: 2533199: Illegal instruction (hart 0) at PC 0x800033a4: 0x3b0e1073
133: 2533239: Illegal instruction (hart 0) at PC 0x800033a4: 0x3b0e1073
[E] 134: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2547449: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80035ce0 was expected
135: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
136:
137:
138: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4273
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4273/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2661265: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4317
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4317/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1016347: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 4f58d000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4336
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
157: 980051: Illegal instruction (hart 0) at PC 0x80003422: 0x74705073
158: 1475451: Illegal instruction (hart 0) at PC 0x8001b000: 0x3a0be073
159: 1475491: Illegal instruction (hart 0) at PC 0x8001b000: 0x3a0be073
160: 1491831: Illegal instruction (hart 0) at PC 0x8001b010: 0x3b049073
161: 1491871: Illegal instruction (hart 0) at PC 0x8001b010: 0x3b049073
[E] 162: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1520761: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 1c2bdd50 but store at address 80035ce0 was expected
163: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
164:
165:
166: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4360
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4360/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 856213: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 3cdc5c00 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4372
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
137: 837932: Illegal instruction (hart 0) at PC 0x80003a88: 0x3a0be073
138: 837952: Illegal instruction (hart 0) at PC 0x80003a88: 0x3a0be073
139: 837952: Illegal instruction (hart 0) at PC 0x80003a88: 0x3a0be073
140: 837972: Illegal instruction (hart 0) at PC 0x80003a88: 0x3a0be073
141: 837992: Illegal instruction (hart 0) at PC 0x80003a88: 0x3a0be073
[E] 142: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 838322: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 6f00000 but store at address 80036ce0 was expected
143: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
144:
145:
146: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4404
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: 965872: Illegal instruction (hart 0) at PC 0x80002c7e: 0x3a096073
114: 999372: Illegal instruction (hart 0) at PC 0x80002c7e: 0x3a096073
115: 999412: Illegal instruction (hart 0) at PC 0x80002c7e: 0x3a096073
116: 1027252: Illegal instruction (hart 0) at PC 0x80002c8e: 0x3b041073
117: 1027292: Illegal instruction (hart 0) at PC 0x80002c8e: 0x3b041073
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1547782: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 4db68a40 but store at address 80035ce0 was expected
119: Synchronous trap was expected at ISS PC: 80001f00 but the DUT didn't report one at PC 80001f82
120:
121:
122: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4423
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4423/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 282356: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 10534100 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4453
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4453/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 31342: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 50000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_epmp_mml_test.3876
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mml_test.3876/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_mml_test.3885
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mml_test.3885/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 7002018: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 7002018: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_mmwp_test.3876
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.3876/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
109:
110: --- RISC-V UVM TEST FAILED ---
111:
112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_mmwp_test.3885
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.3885/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002018: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
109:
110: --- RISC-V UVM TEST FAILED ---
111:
112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002018: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_rlb_test.3876
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_rlb_test.3876/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_rlb_test.3885
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_rlb_test.3885/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002018: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002018: reporter [UVM/REPORT/CATCHER]
--------------------------------------------