Ibex Regression Results

Date/Time run: Wednesday 15 October 2025 04:10 UTC

Git Commit: 1f2232a

Test NamePassingTotalPass Rate
riscv_arithmetic_basic_test 10 10 100.0%
riscv_machine_mode_rand_test 10 10 100.0%
riscv_rand_instr_test 10 10 100.0%
riscv_rand_jump_test 10 10 100.0%
riscv_jump_stress_test 10 10 100.0%
riscv_loop_test 10 10 100.0%
riscv_mmu_stress_test 10 10 100.0%
riscv_illegal_instr_test 15 15 100.0%
riscv_hint_instr_test 10 10 100.0%
riscv_ebreak_test 10 10 100.0%
riscv_debug_basic_test 9 10 90.0%
riscv_debug_triggers_test 5 5 100.0%
riscv_debug_stress_test 15 15 100.0%
riscv_debug_branch_jump_test 10 10 100.0%
riscv_debug_instr_test 25 25 100.0%
riscv_debug_wfi_test 10 10 100.0%
riscv_dret_test 3 5 60.0%
riscv_debug_ebreak_test 14 15 93.3%
riscv_debug_ebreakmu_test 14 15 93.3%
riscv_debug_csr_entry_test 10 10 100.0%
riscv_irq_in_debug_mode_test 10 10 100.0%
riscv_debug_in_irq_test 10 10 100.0%
riscv_assorted_traps_interrupts_debug_test 1 10 10.0%
riscv_single_interrupt_test 15 15 100.0%
riscv_multiple_interrupt_test 10 10 100.0%
riscv_nested_interrupt_test 10 10 100.0%
riscv_interrupt_instr_test 25 25 100.0%
riscv_interrupt_wfi_test 15 15 100.0%
riscv_interrupt_csr_test 10 10 100.0%
riscv_csr_test 5 5 100.0%
riscv_unaligned_load_store_test 5 5 100.0%
riscv_mem_error_test 15 15 100.0%
riscv_mem_intg_error_test 40 50 80.0%
riscv_debug_single_step_test 12 15 80.0%
riscv_reset_test 15 15 100.0%
riscv_pc_intg_test 14 15 93.3%
riscv_rf_intg_test 100 100 100.0%
riscv_rf_ctrl_intg_test 15 15 100.0%
riscv_ram_intg_test 15 15 100.0%
riscv_icache_intg_test 15 15 100.0%
riscv_rv32im_instr_test 5 5 100.0%
riscv_user_mode_rand_test 10 10 100.0%
riscv_umode_tw_test 10 10 100.0%
riscv_invalid_csr_test 10 10 100.0%
riscv_pmp_basic_test 50 50 100.0%
riscv_pmp_disable_all_regions_test 50 50 100.0%
riscv_pmp_out_of_bounds_test 49 50 98.0%
riscv_pmp_full_random_test 568 600 94.7%
riscv_pmp_region_exec_test 20 20 100.0%
riscv_epmp_mml_test 20 20 100.0%
riscv_epmp_mml_execute_only_test 20 20 100.0%
riscv_epmp_mml_read_only_test 20 20 100.0%
riscv_epmp_mmwp_test 19 20 95.0%
riscv_epmp_rlb_test 20 20 100.0%
riscv_bitmanip_otearlgrey_test 10 10 100.0%
riscv_bitmanip_balanced_test 10 10 100.0%
Total 1468 1530 95.9%

Coverage

FunctionalBlockBranchStatementExpressionToggleFSMAssertion
89.7% 95.7% 90.4% 96.9% 90.9% 95.4% 100.0% 98.6%

Test Failure Details

riscv_debug_basic_test.22097
----------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'


riscv_dret_test.22094
---------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    124: 33896: Illegal instruction (hart 0) at PC 0x8000344e: 0x7b200073
    125: 33896: Illegal instruction (hart 0) at PC 0x8000344e: 0x7b200073
    126: 33916: Illegal instruction (hart 0) at PC 0x8000344e: 0x7b200073
    127: 33936: Illegal instruction (hart 0) at PC 0x8000344e: 0x7b200073
    128: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 57546: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 129: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 63106: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
    130: 
    131: --- RISC-V UVM TEST FAILED ---
    132: 
    133: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 63106: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_dret_test.22096
---------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.22096/trace_core_00000000.log
    108: 42402: Illegal instruction (hart 0) at PC 0x80003360: 0x7b200073
    109: 42442: Illegal instruction (hart 0) at PC 0x80003360: 0x7b200073
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 56992: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 64232: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
    112: 
    113: --- RISC-V UVM TEST FAILED ---
    114: 
    115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 64232: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_debug_ebreak_test.22106
-----------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    3111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 58921988: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
    3112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 58923488: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
    3113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 58956308: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
    3114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 58957808: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
    3115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 59001388: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
[E] 3116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 59002028: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    3117: 
    3118: --- RISC-V UVM TEST FAILED ---
    3119: 
    3120: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 59002028: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_debug_ebreakmu_test.22106
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.22106/trace_core_00000000.log
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 43868: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
    111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 45368: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 62002028: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    113: 
    114: --- RISC-V UVM TEST FAILED ---
    115: 
    116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 62002028: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22093
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    4963: 64919759: Illegal instruction (hart 0) at PC 0x000001c8: 0x00000000
    4964: 64941139: Illegal instruction (hart 0) at PC 0x000001cc: 0x00000000
    4965: 64941179: Illegal instruction (hart 0) at PC 0x000001cc: 0x00000000
    4966: 64977199: Illegal instruction (hart 0) at PC 0x000001d0: 0x00000000
    4967: 64977239: Illegal instruction (hart 0) at PC 0x000001d0: 0x00000000
[E] 4968: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 65002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    4969: 
    4970: --- RISC-V UVM TEST FAILED ---
    4971: 
    4972: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 65002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22094
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    960: 9826456: Illegal instruction (hart 0) at PC 0x00000650: 0x00000000
    961: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
    962: IRQs last cycle: 01000, IRQs this cycle: 00000
    963: 9839816: Illegal instruction (hart 0) at PC 0x00000654: 0x00000000
    964: 9839856: Illegal instruction (hart 0) at PC 0x00000654: 0x00000000
[E] 965: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 9839886: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 654 , but the ISS retired: 80002770
    966: 
    967: 
    968: --- RISC-V UVM TEST FAILED ---
    969: 
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22096
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    9465: 12384042: Illegal instruction (hart 0) at PC 0x8000cb36: 0x00000000
    9466: 12392502: Illegal instruction (hart 0) at PC 0x8000cb36: 0x00000000
    9467: 12392542: Illegal instruction (hart 0) at PC 0x8000cb36: 0x00000000
    9468: 12401362: Illegal instruction (hart 0) at PC 0x8000cb36: 0x00000000
    9469: 12401402: Illegal instruction (hart 0) at PC 0x8000cb36: 0x00000000
[E] 9470: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 12409072: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 8000cb24 but load at address 0 was expected
    9471: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000cb0e
    9472: 
    9473: 
    9474: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22097
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    3869: 69927179: Illegal instruction (hart 0) at PC 0xb241a7a8: 0x00000000
    3870: 69948739: Illegal instruction (hart 0) at PC 0xb241a7ac: 0x00000000
    3871: 69948779: Illegal instruction (hart 0) at PC 0xb241a7ac: 0x00000000
    3872: 69977099: Illegal instruction (hart 0) at PC 0xb241a7b0: 0x00000000
    3873: 69977139: Illegal instruction (hart 0) at PC 0xb241a7b0: 0x00000000
[E] 3874: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 70002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    3875: 
    3876: --- RISC-V UVM TEST FAILED ---
    3877: 
    3878: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 70002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22098
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    119: 245496: Illegal instruction (hart 0) at PC 0x8000c086: 0x0000b264
    120: 245536: Illegal instruction (hart 0) at PC 0x8000c086: 0x0000b264
    121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 272946: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/8
    122: 299496: Illegal instruction (hart 0) at PC 0x8000c086: 0x0000b264
    123: 299536: Illegal instruction (hart 0) at PC 0x8000c086: 0x0000b264
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 309206: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffff91c with data a37bc20c but data 0 was expected with byte mask f
    125: Synchronous trap was expected at ISS PC: 80002300 but the DUT didn't report one at PC 8000c89a
    126: 
    127: 
    128: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22099
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    157: 1072093: Illegal instruction (hart 0) at PC 0x8000c032: 0x45f3d967
    158: 1072133: Illegal instruction (hart 0) at PC 0x8000c032: 0x45f3d967
    159: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 1084203: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 5/5
    160: 1096933: Illegal instruction (hart 0) at PC 0x8000c032: 0x45f3d967
    161: 1096973: Illegal instruction (hart 0) at PC 0x8000c032: 0x45f3d967
[E] 162: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1252563: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffe74 with data 9062e7a4 but data 0 was expected with byte mask f
    163: Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000bcd2
    164: 
    165: 
    166: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22100
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 34080: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 0/7
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 34080: uvm_test_top.env.irq_agent.sequencer@@irq_new_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_new_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    115: 151390: Illegal instruction (hart 0) at PC 0x80003702: 0x00003032
    116: 151430: Illegal instruction (hart 0) at PC 0x80003702: 0x00003032
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 225000: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/7
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 300720: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003706
    119: 
    120: 
    121: --- RISC-V UVM TEST FAILED ---
    122: 
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22101
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    368: 5062980: Illegal instruction (hart 0) at PC 0x8000cf32: 0x00000000
    369: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
    370: IRQs last cycle: 20000, IRQs this cycle: 00000
    371: 5080460: Illegal instruction (hart 0) at PC 0x8000cf36: 0x00000000
    372: 5080500: Illegal instruction (hart 0) at PC 0x8000cf36: 0x00000000
[E] 373: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 5080530: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 8000cf36 , but the ISS retired: 8000280c
    374: 
    375: 
    376: --- RISC-V UVM TEST FAILED ---
    377: 
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.22102
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    130: 424657: Illegal instruction (hart 0) at PC 0x8000bf7e: 0x99fd01cf
    131: 424697: Illegal instruction (hart 0) at PC 0x8000bf7e: 0x99fd01cf
    132: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 432547: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 2/4
    133: 442317: Illegal instruction (hart 0) at PC 0x8000bf7e: 0x99fd01cf
    134: 442357: Illegal instruction (hart 0) at PC 0x8000bf7e: 0x99fd01cf
[E] 135: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 444067: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000c9ba
    136: 
    137: 
    138: --- RISC-V UVM TEST FAILED ---
    139: 
--------------------------------------------


riscv_mem_intg_error_test.22100
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13820: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 13820: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 112540: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 166240: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 211980: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 259380: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x31 DUT: 8002bcdc expected: 0
    121: 
    122: 
    123: --- RISC-V UVM TEST FAILED ---
    124: 
--------------------------------------------


riscv_mem_intg_error_test.22108
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 15282: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 15282: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 104182: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 141622: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 238862: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 291662: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x4 DUT: 8001c60a expected: 0
    121: 
    122: 
    123: --- RISC-V UVM TEST FAILED ---
    124: 
--------------------------------------------


riscv_mem_intg_error_test.22117
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22117/trace_core_00000000.log
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 14660: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14660: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 72580: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 124360: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x28 DUT: 8001cb49 expected: 0
    123: 
    124: 
    125: --- RISC-V UVM TEST FAILED ---
    126: 
--------------------------------------------


riscv_mem_intg_error_test.22118
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22118/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 27497: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 27497: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 59877: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 99117: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x16 DUT: 8001a222 expected: 0
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_mem_intg_error_test.22123
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22123/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 31655: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 31655: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 31655: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 79935: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 800176ac expected: 0
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_mem_intg_error_test.22130
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22130/trace_core_00000000.log
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 24626: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 24626: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 24626: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    122: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 112626: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 123: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 154546: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x9 DUT: 8001391c expected: 0
    124: 
    125: 
    126: --- RISC-V UVM TEST FAILED ---
    127: 
--------------------------------------------


riscv_mem_intg_error_test.22131
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22131/trace_core_00000000.log
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 21776: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 21776: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 21776: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 79296: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x19 DUT: 800132b5 expected: 0
    123: 
    124: 
    125: --- RISC-V UVM TEST FAILED ---
    126: 
--------------------------------------------


riscv_mem_intg_error_test.22133
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22133/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 15910: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 15910: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 99890: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 143670: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 800136bc expected: 0
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_mem_intg_error_test.22141
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22141/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 12872: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12872: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 46212: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 105932: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 151792: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x7 DUT: 80013bba expected: 0
    119: 
    120: 
    121: --- RISC-V UVM TEST FAILED ---
    122: 
--------------------------------------------


riscv_mem_intg_error_test.22142
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.22142/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 49289: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 49289: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(176) @ 76609: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 114409: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x28 DUT: 80013622 expected: 0
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_debug_single_step_test.22100
----------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    125: 2839550: Illegal instruction (hart 0) at PC 0x80007a4a: 0xf12ce573
    126: 3477010: Illegal instruction (hart 0) at PC 0x80007a6e: 0x005dd4bb
    127: 3477050: Illegal instruction (hart 0) at PC 0x80007a6e: 0x005dd4bb
    128: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 3556680: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
    129: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 3558180: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 130: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 4737940: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x6 DUT: 140 expected: 100
    131: 
    132: 
    133: --- RISC-V UVM TEST FAILED ---
    134: 
--------------------------------------------


riscv_debug_single_step_test.22101
----------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    122: 1957860: Illegal instruction (hart 0) at PC 0x80003604: 0x7b200073
    123: 1987600: Illegal instruction (hart 0) at PC 0x8000360a: 0x7b200073
    124: 1987640: Illegal instruction (hart 0) at PC 0x8000360a: 0x7b200073
    125: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 2006250: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
    126: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 2007750: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 127: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2025790: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000b9d2
    128: 
    129: 
    130: --- RISC-V UVM TEST FAILED ---
    131: 
--------------------------------------------


riscv_debug_single_step_test.22107
----------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    206: 2420715: Illegal instruction (hart 0) at PC 0x8000bf30: 0xf1379773
    207: 2445415: Illegal instruction (hart 0) at PC 0x8000bf30: 0xf1379773
    208: 2445455: Illegal instruction (hart 0) at PC 0x8000bf30: 0xf1379773
    209: 2476255: Illegal instruction (hart 0) at PC 0x8000bf30: 0xf1379773
    210: 2476295: Illegal instruction (hart 0) at PC 0x8000bf30: 0xf1379773
[E] 211: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2478805: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002ace
    212: 
    213: 
    214: --- RISC-V UVM TEST FAILED ---
    215: 
--------------------------------------------


riscv_pc_intg_test.22095
------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.22095/trace_core_00000000.log not found


riscv_pmp_out_of_bounds_test.22136
----------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
    105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
    106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.22136/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 10002014: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
    111: 
    112: --- RISC-V UVM TEST FAILED ---
    113: 
    114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 10002014: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_pmp_full_random_test.22125
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22125/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 94449: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x24 DUT: 0 expected: ffffffff
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22128
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22128/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 61373: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x5 DUT: 0 expected: ffffffff
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22129
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22129/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 212829: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data e5000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000344e
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22165
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 2010: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22165/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 65670: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 0 expected: ffffffff
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_pmp_full_random_test.22174
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22174/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 115809: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 76000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 800035e8
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22202
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2021: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22202/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 268721: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data e8000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80004ec4
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22220
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    144: 364815: Illegal instruction (hart 0) at PC 0x8001ae78: 0x3b069073
    145: 393375: Illegal instruction (hart 0) at PC 0x8001ae7c: 0x3a09e073
    146: 393415: Illegal instruction (hart 0) at PC 0x8001ae7c: 0x3a09e073
    147: 405415: Illegal instruction (hart 0) at PC 0x8001ae8c: 0x3b069073
    148: 405455: Illegal instruction (hart 0) at PC 0x8001ae8c: 0x3b069073
[E] 149: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 418345: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8001ae92
    150: 
    151: 
    152: --- RISC-V UVM TEST FAILED ---
    153: 
--------------------------------------------


riscv_pmp_full_random_test.22240
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2036: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2036: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2036: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2036: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22240/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 506716: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 1a000000 but data 0 was expected with byte mask 8
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22243
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22243/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 485800: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data e9000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80005268
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22244
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22244/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 269097: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data c9000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80001f00 but the DUT didn't report one at PC 8001add2
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22252
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22252/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 397698: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 12000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004e98
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22253
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    154: 141625: Illegal instruction (hart 0) at PC 0x80005db0: 0x3b071073
    155: 160245: Illegal instruction (hart 0) at PC 0x80005e0e: 0x3a09e073
    156: 160285: Illegal instruction (hart 0) at PC 0x80005e0e: 0x3a09e073
    157: 212645: Illegal instruction (hart 0) at PC 0x80005e1e: 0x3b071073
    158: 212685: Illegal instruction (hart 0) at PC 0x80005e1e: 0x3b071073
[E] 159: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 229375: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 1000000 but data 0 was expected with byte mask 8
    160: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80005e24
    161: 
    162: 
    163: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22272
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22272/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 192049: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data db000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003a8a
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22287
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22287/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1285542: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 3b14c780 with data 83 but data 7a was expected with byte mask 1
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80009076
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22304
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22304/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 42569: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000345e
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22306
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    127: 173346: Illegal instruction (hart 0) at PC 0x800033fe: 0x3b0f1073
    128: 201286: Illegal instruction (hart 0) at PC 0x8000349a: 0x3a0a6073
    129: 201326: Illegal instruction (hart 0) at PC 0x8000349a: 0x3a0a6073
    130: 213526: Illegal instruction (hart 0) at PC 0x800034ac: 0x3b0f1073
    131: 213566: Illegal instruction (hart 0) at PC 0x800034ac: 0x3b0f1073
[E] 132: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 240056: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 70000000 but data 0 was expected with byte mask 8
    133: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003516
    134: 
    135: 
    136: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22321
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22321/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 156949: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 33000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003dd6
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22353
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22353/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 87069: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 800035f4
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22362
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    292: 1181438: Illegal instruction (hart 0) at PC 0x80018ac0: 0x3b091073
    293: 1201698: Illegal instruction (hart 0) at PC 0x80018b90: 0x3a0be073
    294: 1201738: Illegal instruction (hart 0) at PC 0x80018b90: 0x3a0be073
    295: 1226738: Illegal instruction (hart 0) at PC 0x80018ba2: 0x3b091073
    296: 1226778: Illegal instruction (hart 0) at PC 0x80018ba2: 0x3b091073
[E] 297: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1243048: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 3f000000 but data 0 was expected with byte mask 8
    298: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80018c10
    299: 
    300: 
    301: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22363
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22363/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 49645: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 17000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 800089a0
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22364
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 2022: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22364/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 294002: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 85000000 but data 0 was expected with byte mask 8
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_pmp_full_random_test.22366
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22366/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 73209: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 560000 but data 0 was expected with byte mask 4
    113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80003a00
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22417
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22417/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 152942: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000e9e6
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22422
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    143: 298150: Illegal instruction (hart 0) at PC 0x80003904: 0x3a0b6073
    144: 298170: Illegal instruction (hart 0) at PC 0x80003904: 0x3a0b6073
    145: 298190: Illegal instruction (hart 0) at PC 0x80003904: 0x3a0b6073
    146: 319330: Illegal instruction (hart 0) at PC 0x80003916: 0x3b0f1073
    147: 319370: Illegal instruction (hart 0) at PC 0x80003916: 0x3b0f1073
[E] 148: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 331300: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 48000000 but data 0 was expected with byte mask 8
    149: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000391c
    150: 
    151: 
    152: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22430
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 2022: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22430/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 110942: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x9 DUT: 0 expected: ffffffff
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_pmp_full_random_test.22463
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22463/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 171539: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 35000000 but data 0 was expected with byte mask 8
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_pmp_full_random_test.22496
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22496/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1447729: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address fffffffc but store at address 80036ce0 was expected
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22512
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    275: 560729: Illegal instruction (hart 0) at PC 0x80004242: 0x3a08e073
    276: 597049: Illegal instruction (hart 0) at PC 0x80004254: 0x3b0b1073
    277: 597089: Illegal instruction (hart 0) at PC 0x80004254: 0x3b0b1073
    278: 641829: Illegal instruction (hart 0) at PC 0x80004418: 0x3a0ae073
    279: 641869: Illegal instruction (hart 0) at PC 0x80004418: 0x3a0ae073
[E] 280: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 641879: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004414
    281: 
    282: 
    283: --- RISC-V UVM TEST FAILED ---
    284: 
--------------------------------------------


riscv_pmp_full_random_test.22558
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22558/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 3300275: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 69000000 but data 0 was expected with byte mask 8
    113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80016a54
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22587
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 2024: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22587/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 37464: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000359e
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_pmp_full_random_test.22595
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(192) @ 2026: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
    113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22595/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 315986: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 870000 but data 0 was expected with byte mask 4
    118: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 800045b6
    119: 
    120: 
    121: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.22691
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.22691/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 82479: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 89000000 but data 0 was expected with byte mask 8
    113: 
    114: 
    115: --- RISC-V UVM TEST FAILED ---
    116: 
--------------------------------------------


riscv_epmp_mmwp_test.22111
--------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
    103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
    104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.22111/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 12002026: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
    109: 
    110: --- RISC-V UVM TEST FAILED ---
    111: 
    112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 12002026: reporter [UVM/REPORT/CATCHER]
--------------------------------------------