Ibex Regression Results
Date/Time run: Monday 28 April 2025 04:08 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
10 |
10 |
100.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
15 |
15 |
100.0% |
| riscv_hint_instr_test |
10 |
10 |
100.0% |
| riscv_ebreak_test |
10 |
10 |
100.0% |
| riscv_debug_basic_test |
9 |
10 |
90.0% |
| riscv_debug_triggers_test |
5 |
5 |
100.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
10 |
10 |
100.0% |
| riscv_debug_instr_test |
25 |
25 |
100.0% |
| riscv_debug_wfi_test |
10 |
10 |
100.0% |
| riscv_dret_test |
2 |
5 |
40.0% |
| riscv_debug_ebreak_test |
15 |
15 |
100.0% |
| riscv_debug_ebreakmu_test |
13 |
15 |
86.7% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
10 |
10 |
100.0% |
| riscv_debug_in_irq_test |
10 |
10 |
100.0% |
| riscv_assorted_traps_interrupts_debug_test |
4 |
10 |
40.0% |
| riscv_single_interrupt_test |
15 |
15 |
100.0% |
| riscv_multiple_interrupt_test |
10 |
10 |
100.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
14 |
15 |
93.3% |
| riscv_mem_intg_error_test |
43 |
50 |
86.0% |
| riscv_debug_single_step_test |
14 |
15 |
93.3% |
| riscv_reset_test |
15 |
15 |
100.0% |
| riscv_pc_intg_test |
13 |
15 |
86.7% |
| riscv_rf_intg_test |
100 |
100 |
100.0% |
| riscv_rf_ctrl_intg_test |
15 |
15 |
100.0% |
| riscv_ram_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
15 |
15 |
100.0% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
50 |
50 |
100.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
49 |
50 |
98.0% |
| riscv_pmp_full_random_test |
599 |
600 |
99.8% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
20 |
20 |
100.0% |
| riscv_epmp_rlb_test |
20 |
20 |
100.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| Total |
1505 |
1530 |
98.4% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 94.1% |
95.7% |
90.4% |
97.1% |
90.9% |
97.2% |
100.0% |
98.7% |
Test Failure Details
riscv_debug_basic_test.5271
---------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_basic_test.5271/trace_core_00000000.log
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 32452: reporter@@debug_seq_stress_h [debug_seq_stress_h] Starting sequence...
[E] 113: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 17932412: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80000000 , but the ISS retired: ffffffff80006886
114:
115:
116: --- RISC-V UVM TEST FAILED ---
117:
--------------------------------------------
riscv_dret_test.5265
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.5265/trace_core_00000000.log
108: 128007: Illegal instruction (hart 0) at PC 0x8000beb2: 0x7b200073
109: 128047: Illegal instruction (hart 0) at PC 0x8000beb2: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 144797: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 150537: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 150537: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.5266
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
124: 35044: Illegal instruction (hart 0) at PC 0x8000330e: 0x7b200073
125: 35044: Illegal instruction (hart 0) at PC 0x8000330e: 0x7b200073
126: 35064: Illegal instruction (hart 0) at PC 0x8000330e: 0x7b200073
127: 35084: Illegal instruction (hart 0) at PC 0x8000330e: 0x7b200073
128: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 61194: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 129: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 65874: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
130:
131: --- RISC-V UVM TEST FAILED ---
132:
133: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 65874: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.5267
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.5267/trace_core_00000000.log
108: 162174: Illegal instruction (hart 0) at PC 0x800051b8: 0x7b200073
109: 162214: Illegal instruction (hart 0) at PC 0x800051b8: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 176984: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 183844: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 183844: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.5264
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.5264/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1746) @ 35080: uvm_test_top [uvm_test_top] EBreak seen whilst doing initial debug initialization, KNOWN FAILURE SEE https://github.com/lowRISC/ibex/issues/1313
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 35080: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.5268
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(183) @ 2021: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
114: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.5268/trace_core_00000000.log
[E] 115: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1746) @ 29581: uvm_test_top [uvm_test_top] EBreak seen whilst doing initial debug initialization, KNOWN FAILURE SEE https://github.com/lowRISC/ibex/issues/1313
116:
117: --- RISC-V UVM TEST FAILED ---
118:
119: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 29581: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5263
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1441: 25202214: Illegal instruction (hart 0) at PC 0x880eeef4: 0x00000000
1442: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
1443: IRQs last cycle: 00010, IRQs this cycle: 00000
1444: 25235334: Illegal instruction (hart 0) at PC 0x880eeef8: 0x00000000
1445: 25235374: Illegal instruction (hart 0) at PC 0x880eeef8: 0x00000000
[E] 1446: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 25235404: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 880eeef8 , but the ISS retired: 80002050
1447:
1448:
1449: --- RISC-V UVM TEST FAILED ---
1450:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5264
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
647: 6899910: Illegal instruction (hart 0) at PC 0x000dfbcc: 0x00000000
648: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
649: IRQs last cycle: 00080, IRQs this cycle: 00000
650: 6920510: Illegal instruction (hart 0) at PC 0x000dfbd0: 0x00000000
651: 6920550: Illegal instruction (hart 0) at PC 0x000dfbd0: 0x00000000
[E] 652: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 6920580: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : dfbd0 , but the ISS retired: 8000255c
653:
654:
655: --- RISC-V UVM TEST FAILED ---
656:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5265
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
140: 672787: Illegal instruction (hart 0) at PC 0x8000bcf2: 0x00003170
141: 690047: Illegal instruction (hart 0) at PC 0x8000bcf2: 0x00003170
142: 690087: Illegal instruction (hart 0) at PC 0x8000bcf2: 0x00003170
143: 719527: Illegal instruction (hart 0) at PC 0x8000bcf2: 0x00003170
144: 719567: Illegal instruction (hart 0) at PC 0x8000bcf2: 0x00003170
[E] 145: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 27002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
146:
147: --- RISC-V UVM TEST FAILED ---
148:
149: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 27002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5268
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
371: 4652771: Illegal instruction (hart 0) at PC 0x6ca1b25e: 0x00000000
372: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
373: IRQs last cycle: 04000, IRQs this cycle: 00000
374: 4704771: Illegal instruction (hart 0) at PC 0x6ca1b262: 0x00000000
375: 4704811: Illegal instruction (hart 0) at PC 0x6ca1b262: 0x00000000
[E] 376: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 4704841: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 6ca1b262 , but the ISS retired: 80002778
377:
378:
379: --- RISC-V UVM TEST FAILED ---
380:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5271
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4403: 68948942: Illegal instruction (hart 0) at PC 0xbb3d8996: 0x00000000
4404: 68975462: Illegal instruction (hart 0) at PC 0xbb3d899a: 0x00000000
4405: 68975502: Illegal instruction (hart 0) at PC 0xbb3d899a: 0x00000000
4406: 68998782: Illegal instruction (hart 0) at PC 0xbb3d899e: 0x00000000
4407: 68998822: Illegal instruction (hart 0) at PC 0xbb3d899e: 0x00000000
[E] 4408: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 69002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4409:
4410: --- RISC-V UVM TEST FAILED ---
4411:
4412: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 69002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.5272
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4798: 62923892: Illegal instruction (hart 0) at PC 0x20a0de50: 0x00000000
4799: 62962212: Illegal instruction (hart 0) at PC 0x20a0de54: 0x00000000
4800: 62962252: Illegal instruction (hart 0) at PC 0x20a0de54: 0x00000000
4801: 62994472: Illegal instruction (hart 0) at PC 0x20a0de58: 0x00000000
4802: 62994512: Illegal instruction (hart 0) at PC 0x20a0de58: 0x00000000
[E] 4803: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 63002022: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4804:
4805: --- RISC-V UVM TEST FAILED ---
4806:
4807: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 63002022: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_mem_error_test.5263
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
420: 6604574: Illegal instruction (hart 0) at PC 0x8000f864: 0xf13c3df3
421: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 6630124: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
422: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 6696344: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
423: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 6769244: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
424: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 6853644: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 425: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 6854504: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80002400 , but the ISS retired: ffffffff80002480
426:
427:
428: --- RISC-V UVM TEST FAILED ---
429:
--------------------------------------------
riscv_mem_intg_error_test.5263
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.5263/trace_core_00000000.log
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 24144: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 24144: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 89544: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
122: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 185824: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 123: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 234644: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x4 DUT: 800227f3 expected: 0
124:
125:
126: --- RISC-V UVM TEST FAILED ---
127:
--------------------------------------------
riscv_mem_intg_error_test.5267
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 12664: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 80104: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 178924: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 229144: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 278184: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 121: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 324024: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x8 DUT: 8001ece3 expected: 0
122:
123:
124: --- RISC-V UVM TEST FAILED ---
125:
--------------------------------------------
riscv_mem_intg_error_test.5269
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.5269/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 13418: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13418: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 13418: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 47738: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x15 DUT: 80013e44 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.5271
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.5271/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 17392: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 17392: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 105032: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 141252: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x19 DUT: 80012f2d expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.5285
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 268168: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
122: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 327728: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
123: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 366548: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
124: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 382788: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
125: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 400828: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 126: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 421368: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x24 DUT: 800136d8 expected: 0
127:
128:
129: --- RISC-V UVM TEST FAILED ---
130:
--------------------------------------------
riscv_mem_intg_error_test.5304
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.5304/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 13902: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13902: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 84062: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 137142: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x7 DUT: 8001bd6c expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.5306
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.5306/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 39596: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 39596: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 93236: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 131536: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 800135df expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_debug_single_step_test.5267
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
455: 15627074: Illegal instruction (hart 0) at PC 0x000001c0: 0x00000000
456: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 15633944: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
457: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 15635444: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
458: 15990554: Illegal instruction (hart 0) at PC 0x00000000: 0x00000000
459: 15990594: Illegal instruction (hart 0) at PC 0x00000000: 0x00000000
[E] 460: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 15990624: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x1, but a write was expected
461:
462:
463: --- RISC-V UVM TEST FAILED ---
464:
--------------------------------------------
riscv_pc_intg_test.5270
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.5270/trace_core_00000000.log not found
riscv_pc_intg_test.5272
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.5272/trace_core_00000000.log not found
riscv_pmp_out_of_bounds_test.5295
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(183) @ 2024: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
114: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.5295/trace_core_00000000.log
[E] 115: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 10002024: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
116:
117: --- RISC-V UVM TEST FAILED ---
118:
119: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 10002024: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.5664
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
729: 3142347: Illegal instruction (hart 0) at PC 0x800089b4: 0x3b041073
730: 3176347: Illegal instruction (hart 0) at PC 0x80008abc: 0x3a0b6073
731: 3176387: Illegal instruction (hart 0) at PC 0x80008abc: 0x3a0b6073
732: 3199087: Illegal instruction (hart 0) at PC 0x80008acc: 0x3b041073
733: 3199127: Illegal instruction (hart 0) at PC 0x80008acc: 0x3b041073
[E] 734: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 3249917: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 197c8000 with data 0 but data be was expected with byte mask 1
735: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80008b40
736:
737:
738: --- RISC-V UVM TEST FAILED ---
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