Ibex Regression Results
Date/Time run: Tuesday 29 October 2024 04:07 UTC
Test Name | Passing | Total | Pass Rate |
riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
riscv_rand_instr_test |
10 |
10 |
100.0% |
riscv_rand_jump_test |
10 |
10 |
100.0% |
riscv_jump_stress_test |
10 |
10 |
100.0% |
riscv_loop_test |
10 |
10 |
100.0% |
riscv_mmu_stress_test |
10 |
10 |
100.0% |
riscv_illegal_instr_test |
15 |
15 |
100.0% |
riscv_hint_instr_test |
10 |
10 |
100.0% |
riscv_ebreak_test |
10 |
10 |
100.0% |
riscv_debug_basic_test |
10 |
10 |
100.0% |
riscv_debug_triggers_test |
5 |
5 |
100.0% |
riscv_debug_stress_test |
15 |
15 |
100.0% |
riscv_debug_branch_jump_test |
10 |
10 |
100.0% |
riscv_debug_instr_test |
25 |
25 |
100.0% |
riscv_debug_wfi_test |
10 |
10 |
100.0% |
riscv_dret_test |
4 |
5 |
80.0% |
riscv_debug_ebreak_test |
15 |
15 |
100.0% |
riscv_debug_ebreakmu_test |
14 |
15 |
93.3% |
riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
riscv_irq_in_debug_mode_test |
10 |
10 |
100.0% |
riscv_debug_in_irq_test |
10 |
10 |
100.0% |
riscv_assorted_traps_interrupts_debug_test |
3 |
10 |
30.0% |
riscv_single_interrupt_test |
14 |
15 |
93.3% |
riscv_multiple_interrupt_test |
9 |
10 |
90.0% |
riscv_nested_interrupt_test |
10 |
10 |
100.0% |
riscv_interrupt_instr_test |
25 |
25 |
100.0% |
riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
riscv_interrupt_csr_test |
10 |
10 |
100.0% |
riscv_csr_test |
5 |
5 |
100.0% |
riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
riscv_mem_error_test |
14 |
15 |
93.3% |
riscv_mem_intg_error_test |
46 |
50 |
92.0% |
riscv_debug_single_step_test |
10 |
15 |
66.7% |
riscv_reset_test |
15 |
15 |
100.0% |
riscv_pc_intg_test |
13 |
15 |
86.7% |
riscv_rf_intg_test |
100 |
100 |
100.0% |
riscv_rf_ctrl_intg_test |
15 |
15 |
100.0% |
riscv_ram_intg_test |
15 |
15 |
100.0% |
riscv_icache_intg_test |
15 |
15 |
100.0% |
riscv_rv32im_instr_test |
5 |
5 |
100.0% |
riscv_user_mode_rand_test |
10 |
10 |
100.0% |
riscv_umode_tw_test |
10 |
10 |
100.0% |
riscv_invalid_csr_test |
10 |
10 |
100.0% |
riscv_pmp_basic_test |
49 |
50 |
98.0% |
riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
riscv_pmp_out_of_bounds_test |
50 |
50 |
100.0% |
riscv_pmp_full_random_test |
598 |
600 |
99.7% |
riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
riscv_epmp_mml_test |
19 |
20 |
95.0% |
riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
riscv_epmp_mmwp_test |
18 |
20 |
90.0% |
riscv_epmp_rlb_test |
20 |
20 |
100.0% |
riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
Total |
1501 |
1530 |
98.1% |
Coverage
Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
94.1% |
95.9% |
90.6% |
95.9% |
90.8% |
97.2% |
100.0% |
98.1% |
Test Failure Details
riscv_dret_test.31439
---------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.31439/trace_core_00000000.log
108: 64224: Illegal instruction (hart 0) at PC 0x8000374e: 0x7b200073
109: 64264: Illegal instruction (hart 0) at PC 0x8000374e: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 92654: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 107414: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 107414: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.31450
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.31450/trace_core_00000000.log
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 25687: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 27187: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 63002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 63002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31436
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4094: 63941560: Illegal instruction (hart 0) at PC 0x00002e8e: 0x00010413
4095: 63961180: Illegal instruction (hart 0) at PC 0x00002e92: 0x00010413
4096: 63961220: Illegal instruction (hart 0) at PC 0x00002e92: 0x00010413
4097: 63988080: Illegal instruction (hart 0) at PC 0x00002e96: 0x00010413
4098: 63988120: Illegal instruction (hart 0) at PC 0x00002e96: 0x00010413
[E] 4099: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 64002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4100:
4101: --- RISC-V UVM TEST FAILED ---
4102:
4103: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 64002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31437
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
3647: 65932517: Illegal instruction (hart 0) at PC 0x239a2d1a: 0x00010413
3648: 65984697: Illegal instruction (hart 0) at PC 0x239a2d1e: 0x00010413
3649: 65984737: Illegal instruction (hart 0) at PC 0x239a2d1e: 0x00010413
3650: 65996157: Illegal instruction (hart 0) at PC 0x239a2d22: 0x00010413
3651: 65996197: Illegal instruction (hart 0) at PC 0x239a2d22: 0x00010413
[E] 3652: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 66002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
3653:
3654: --- RISC-V UVM TEST FAILED ---
3655:
3656: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 66002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31439
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
184: 2218304: Illegal instruction (hart 0) at PC 0x800069ec: 0x03cd663b
185: 2218344: Illegal instruction (hart 0) at PC 0x800069ec: 0x03cd663b
186: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
187: IRQs last cycle: 20000, IRQs this cycle: 00000
188: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/rtl/ibex_controller.sv,995): (time 2246334 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 189: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/rtl/ibex_controller.sv(995) @ 2246334: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
190:
191: --- RISC-V UVM TEST FAILED ---
192:
193: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 2246334: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31440
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
4097: 59294721: Illegal instruction (hart 0) at PC 0x281485bc: 0x00010413
4098: 59306901: Illegal instruction (hart 0) at PC 0x281485c0: 0x00010413
4099: 59306941: Illegal instruction (hart 0) at PC 0x281485c0: 0x00010413
4100: 59354461: Illegal instruction (hart 0) at PC 0x281485c4: 0x00010413
4101: 59354501: Illegal instruction (hart 0) at PC 0x281485c4: 0x00010413
[E] 4102: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 59377071: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 1800 expected: 0
4103:
4104:
4105: --- RISC-V UVM TEST FAILED ---
4106:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31442
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
229: 2725995: Illegal instruction (hart 0) at PC 0x82aef33c: 0x00010413
230: 2765555: Illegal instruction (hart 0) at PC 0x82aef340: 0x00010413
231: 2765595: Illegal instruction (hart 0) at PC 0x82aef340: 0x00010413
232: 2776735: Illegal instruction (hart 0) at PC 0x82aef344: 0x00010413
233: 2776775: Illegal instruction (hart 0) at PC 0x82aef344: 0x00010413
[E] 234: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2776805: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x10, but a write was expected
235:
236:
237: --- RISC-V UVM TEST FAILED ---
238:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31444
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
3857: 64915442: Illegal instruction (hart 0) at PC 0x00001cb4: 0x00010413
3858: 64940342: Illegal instruction (hart 0) at PC 0x00001cb8: 0x00010413
3859: 64940382: Illegal instruction (hart 0) at PC 0x00001cb8: 0x00010413
3860: 64971182: Illegal instruction (hart 0) at PC 0x00001cbc: 0x00010413
3861: 64971222: Illegal instruction (hart 0) at PC 0x00001cbc: 0x00010413
[E] 3862: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 65002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
3863:
3864: --- RISC-V UVM TEST FAILED ---
3865:
3866: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 65002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.31445
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1016: 17433039: Illegal instruction (hart 0) at PC 0x8dbf8c40: 0x00010413
1017: 17433079: Illegal instruction (hart 0) at PC 0x8dbf8c40: 0x00010413
1018: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
1019: IRQs last cycle: 00000, IRQs this cycle: 00000
1020: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/rtl/ibex_controller.sv,995): (time 17459209 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 1021: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/rtl/ibex_controller.sv(995) @ 17459209: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
1022:
1023: --- RISC-V UVM TEST FAILED ---
1024:
1025: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 17459209: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_single_interrupt_test.31439
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
188: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 189134: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Stopping sequence
189: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 189134: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Stopping sequence
190: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 189144: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Exiting sequence
191: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(822) @ 189174: uvm_test_top [uvm_test_top] irq: 0x4000000
192: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(825) @ 189174: uvm_test_top [uvm_test_top] irq_id: 0x1a
[E] 193: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(429) @ 200474: reporter [uvm_test_top] Check failed signature_data == core_status (8 [0x8] vs 6 [0x6]) Core did not jump to vectored interrupt handler
194:
195: --- RISC-V UVM TEST FAILED ---
196:
197: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 200474: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_multiple_interrupt_test.31444
-----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
15113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 61966422: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
15114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 61976892: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Starting sequence...
15115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 61976902: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Exiting sequence
15116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(822) @ 61976932: uvm_test_top [uvm_test_top] irq: 0x7fe00008
15117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(825) @ 61976932: uvm_test_top [uvm_test_top] irq_id: 0x16
[E] 15118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 62002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
15119:
15120: --- RISC-V UVM TEST FAILED ---
15121:
15122: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 62002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_mem_error_test.31450
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1356: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 20685607: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
1357: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 20779387: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
1358: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 20846667: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
1359: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 20900127: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
1360: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 20928147: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 1361: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 20929507: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80002100 , but the ISS retired: ffffffff80002180
1362:
1363:
1364: --- RISC-V UVM TEST FAILED ---
1365:
--------------------------------------------
riscv_mem_intg_error_test.31460
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.31460/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 10822: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 10822: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 10822: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 55222: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x9 DUT: 80028e3c expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.31465
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.31465/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 14180: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14180: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 59440: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 92520: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 8001fb51 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.31480
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.31480/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 28133: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 28133: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 72633: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 101913: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 143193: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x28 DUT: 80018e00 expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.31481
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2030: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.31481/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 13690: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13690: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 49930: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 93470: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x30 DUT: 80013567 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_debug_single_step_test.31440
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
1683: 3020101: Illegal instruction (hart 0) at PC 0x40000178: 0x00010413
1684: 3043121: Illegal instruction (hart 0) at PC 0x40000180: 0x00010413
1685: 3043161: Illegal instruction (hart 0) at PC 0x40000180: 0x00010413
1686: 3054401: Illegal instruction (hart 0) at PC 0x40000184: 0x00010413
1687: 3054441: Illegal instruction (hart 0) at PC 0x40000184: 0x00010413
[E] 1688: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 3054471: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x3, but a write was expected
1689:
1690:
1691: --- RISC-V UVM TEST FAILED ---
1692:
--------------------------------------------
riscv_debug_single_step_test.31441
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
171: 5847858: Illegal instruction (hart 0) at PC 0x80007312: 0xf13c39f3
172: 5864138: Illegal instruction (hart 0) at PC 0x80007320: 0x7b200073
173: 5864178: Illegal instruction (hart 0) at PC 0x80007320: 0x7b200073
174: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 5879848: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
175: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 5881348: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 176: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 6011448: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch A load at address 80020094 was expected but there are no pending accesses
177: Synchronous trap was expected at ISS PC: 80000000 but the DUT didn't report one at PC 80000000
178:
179:
180: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_debug_single_step_test.31446
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
564: 22809276: Illegal instruction (hart 0) at PC 0x8000bc4c: 0x8000288e
565: 22809296: Illegal instruction (hart 0) at PC 0x8000bc4c: 0x8000288e
566: 22809316: Illegal instruction (hart 0) at PC 0x8000bc4c: 0x8000288e
567: 22813616: Illegal instruction (hart 0) at PC 0x8000bc4c: 0x8000288e
568: 22813656: Illegal instruction (hart 0) at PC 0x8000bc4c: 0x8000288e
[E] 569: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 22813666: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000004 but the DUT didn't report one at PC 8000bc48
570:
571:
572: --- RISC-V UVM TEST FAILED ---
573:
--------------------------------------------
riscv_debug_single_step_test.31447
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
145: 3686173: Illegal instruction (hart 0) at PC 0x40000122: 0x00010413
146: 3699993: Illegal instruction (hart 0) at PC 0x40000126: 0x00010413
147: 3700033: Illegal instruction (hart 0) at PC 0x40000126: 0x00010413
148: 3711613: Illegal instruction (hart 0) at PC 0x4000012a: 0x00010413
149: 3711653: Illegal instruction (hart 0) at PC 0x4000012a: 0x00010413
[E] 150: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 3711683: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x8, but a write was expected
151:
152:
153: --- RISC-V UVM TEST FAILED ---
154:
--------------------------------------------
riscv_debug_single_step_test.31449
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
72354: 73998940: Illegal instruction (hart 0) at PC 0x8000c27c: 0x00010613
72355: 74000120: Illegal instruction (hart 0) at PC 0x8000c27c: 0x00010613
72356: 74000160: Illegal instruction (hart 0) at PC 0x8000c27c: 0x00010613
72357: 74001300: Illegal instruction (hart 0) at PC 0x8000c27c: 0x00010613
72358: 74001340: Illegal instruction (hart 0) at PC 0x8000c27c: 0x00010613
[E] 72359: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 74002030: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
72360:
72361: --- RISC-V UVM TEST FAILED ---
72362:
72363: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 74002030: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pc_intg_test.31441
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.31441/trace_core_00000000.log not found
riscv_pc_intg_test.31448
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.31448/trace_core_00000000.log not found
riscv_pmp_basic_test.31450
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.31450/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 11002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.31528
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.31528/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 443056: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 3d680000 with data fd but data 65 was expected with byte mask 1
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000bf14
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.31681
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.31681/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 882958: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 75b0ade0 with data e3 but data 7d was expected with byte mask 1
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003900
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_epmp_mml_test.31450
-------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mml_test.31450/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 11002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_mmwp_test.31450
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.31450/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 11002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
109:
110: --- RISC-V UVM TEST FAILED ---
111:
112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_epmp_mmwp_test.31453
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2010: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.31453/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 11002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
109:
110: --- RISC-V UVM TEST FAILED ---
111:
112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------