Ibex Regression Results

Date/Time run: Friday 27 June 2025 04:14 UTC

Git Commit: f0d408a

Test NamePassingTotalPass Rate
riscv_arithmetic_basic_test 10 10 100.0%
riscv_machine_mode_rand_test 10 10 100.0%
riscv_rand_instr_test 10 10 100.0%
riscv_rand_jump_test 9 10 90.0%
riscv_jump_stress_test 10 10 100.0%
riscv_loop_test 10 10 100.0%
riscv_mmu_stress_test 10 10 100.0%
riscv_illegal_instr_test 15 15 100.0%
riscv_hint_instr_test 10 10 100.0%
riscv_ebreak_test 10 10 100.0%
riscv_debug_basic_test 9 10 90.0%
riscv_debug_triggers_test 5 5 100.0%
riscv_debug_stress_test 15 15 100.0%
riscv_debug_branch_jump_test 10 10 100.0%
riscv_debug_instr_test 25 25 100.0%
riscv_debug_wfi_test 10 10 100.0%
riscv_dret_test 3 5 60.0%
riscv_debug_ebreak_test 15 15 100.0%
riscv_debug_ebreakmu_test 15 15 100.0%
riscv_debug_csr_entry_test 10 10 100.0%
riscv_irq_in_debug_mode_test 10 10 100.0%
riscv_debug_in_irq_test 10 10 100.0%
riscv_assorted_traps_interrupts_debug_test 5 10 50.0%
riscv_single_interrupt_test 15 15 100.0%
riscv_multiple_interrupt_test 10 10 100.0%
riscv_nested_interrupt_test 10 10 100.0%
riscv_interrupt_instr_test 25 25 100.0%
riscv_interrupt_wfi_test 15 15 100.0%
riscv_interrupt_csr_test 10 10 100.0%
riscv_csr_test 5 5 100.0%
riscv_unaligned_load_store_test 5 5 100.0%
riscv_mem_error_test 14 15 93.3%
riscv_mem_intg_error_test 46 50 92.0%
riscv_debug_single_step_test 15 15 100.0%
riscv_reset_test 15 15 100.0%
riscv_pc_intg_test 12 15 80.0%
riscv_rf_intg_test 100 100 100.0%
riscv_rf_ctrl_intg_test 15 15 100.0%
riscv_ram_intg_test 15 15 100.0%
riscv_icache_intg_test 15 15 100.0%
riscv_rv32im_instr_test 5 5 100.0%
riscv_user_mode_rand_test 10 10 100.0%
riscv_umode_tw_test 10 10 100.0%
riscv_invalid_csr_test 10 10 100.0%
riscv_pmp_basic_test 50 50 100.0%
riscv_pmp_disable_all_regions_test 50 50 100.0%
riscv_pmp_out_of_bounds_test 50 50 100.0%
riscv_pmp_full_random_test 598 600 99.7%
riscv_pmp_region_exec_test 20 20 100.0%
riscv_epmp_mml_test 20 20 100.0%
riscv_epmp_mml_execute_only_test 20 20 100.0%
riscv_epmp_mml_read_only_test 20 20 100.0%
riscv_epmp_mmwp_test 20 20 100.0%
riscv_epmp_rlb_test 20 20 100.0%
riscv_bitmanip_otearlgrey_test 10 10 100.0%
riscv_bitmanip_balanced_test 10 10 100.0%
Total 1511 1530 98.8%

Coverage

FunctionalBlockBranchStatementExpressionToggleFSMAssertion
89.5% 95.7% 90.3% 97.0% 90.9% 97.3% 100.0% 98.7%

Test Failure Details

riscv_rand_jump_test.10338
--------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
    102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.10338/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 68002013: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    107: 
    108: --- RISC-V UVM TEST FAILED ---
    109: 
    110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 68002013: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_debug_basic_test.10342
----------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    528: 16900364: Illegal instruction (hart 0) at PC 0x80000444: 0x34202f73
    529: 16900384: Illegal instruction (hart 0) at PC 0x80000444: 0x34202f73
    530: 16900404: Illegal instruction (hart 0) at PC 0x80000444: 0x34202f73
    531: 16991464: Illegal instruction (hart 0) at PC 0x80000444: 0x34202f73
    532: 16991504: Illegal instruction (hart 0) at PC 0x80000444: 0x34202f73
[E] 533: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1027) @ 16997894: uvm_test_top [uvm_test_top] No dret detected, or incorrect privilege mode switch in timeout period of 100000 cycles
    534: 
    535: --- RISC-V UVM TEST FAILED ---
    536: 
    537: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 16997894: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_dret_test.10333
---------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    112: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.10333/trace_core_00000000.log
    113: 40245: Illegal instruction (hart 0) at PC 0x800032e8: 0x7b200073
    114: 40285: Illegal instruction (hart 0) at PC 0x800032e8: 0x7b200073
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 52475: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 59235: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
    117: 
    118: --- RISC-V UVM TEST FAILED ---
    119: 
    120: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 59235: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_dret_test.10334
---------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    122: 29542: Illegal instruction (hart 0) at PC 0x800034f2: 0x7b200073
    123: 29542: Illegal instruction (hart 0) at PC 0x800034f2: 0x7b200073
    124: 29562: Illegal instruction (hart 0) at PC 0x800034f2: 0x7b200073
    125: 29582: Illegal instruction (hart 0) at PC 0x800034f2: 0x7b200073
    126: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(973) @ 48512: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 127: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1038) @ 54712: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
    128: 
    129: --- RISC-V UVM TEST FAILED ---
    130: 
    131: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 54712: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.10333
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    805: 8464565: Illegal instruction (hart 0) at PC 0x00000c84: 0x00000000
    806: 8478285: Illegal instruction (hart 0) at PC 0x00000c88: 0x00000000
    807: 8478325: Illegal instruction (hart 0) at PC 0x00000c88: 0x00000000
    808: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
    809: IRQs last cycle: 00000, IRQs this cycle: 00000
[E] 810: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 8498935: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 8000d262 , but the ISS retired: 8000287c
    811: 
    812: 
    813: --- RISC-V UVM TEST FAILED ---
    814: 
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.10334
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    4199: 70884862: Illegal instruction (hart 0) at PC 0x00001f10: 0x00000000
    4200: 70909042: Illegal instruction (hart 0) at PC 0x00001f14: 0x00000000
    4201: 70909082: Illegal instruction (hart 0) at PC 0x00001f14: 0x00000000
    4202: 70931182: Illegal instruction (hart 0) at PC 0x00001f18: 0x00000000
    4203: 70931222: Illegal instruction (hart 0) at PC 0x00001f18: 0x00000000
[E] 4204: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 71002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    4205: 
    4206: --- RISC-V UVM TEST FAILED ---
    4207: 
    4208: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 71002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.10336
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    146: 499456: Illegal instruction (hart 0) at PC 0x8000bbf0: 0xf693fdcf
    147: 545936: Illegal instruction (hart 0) at PC 0x80006a32: 0xde4688f3
    148: 545976: Illegal instruction (hart 0) at PC 0x80006a32: 0xde4688f3
    149: 619896: Illegal instruction (hart 0) at PC 0x80006bdc: 0x000061fc
    150: 619936: Illegal instruction (hart 0) at PC 0x80006bdc: 0x000061fc
[E] 151: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 646666: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 1800 expected: 80
    152: 
    153: 
    154: --- RISC-V UVM TEST FAILED ---
    155: 
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.10339
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    4823: 72806720: Illegal instruction (hart 0) at PC 0x40001c02: 0x00000000
    4824: 72904160: Illegal instruction (hart 0) at PC 0x40001c06: 0x00000000
    4825: 72904200: Illegal instruction (hart 0) at PC 0x40001c06: 0x00000000
    4826: 72971500: Illegal instruction (hart 0) at PC 0x40001c0a: 0x00000000
    4827: 72971540: Illegal instruction (hart 0) at PC 0x40001c0a: 0x00000000
[E] 4828: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 73002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    4829: 
    4830: --- RISC-V UVM TEST FAILED ---
    4831: 
    4832: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 73002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_assorted_traps_interrupts_debug_test.10340
------------------------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
    4466: 71922877: Illegal instruction (hart 0) at PC 0x800e5fa2: 0x00000000
    4467: 71979137: Illegal instruction (hart 0) at PC 0x800e5fa6: 0x00000000
    4468: 71979177: Illegal instruction (hart 0) at PC 0x800e5fa6: 0x00000000
    4469: 71992077: Illegal instruction (hart 0) at PC 0x800e5faa: 0x00000000
    4470: 71992117: Illegal instruction (hart 0) at PC 0x800e5faa: 0x00000000
[E] 4471: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(337) @ 72002027: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
    4472: 
    4473: --- RISC-V UVM TEST FAILED ---
    4474: 
    4475: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 72002027: reporter [UVM/REPORT/CATCHER]
--------------------------------------------


riscv_mem_error_test.10343
--------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    822: 12989921: Illegal instruction (hart 0) at PC 0x80007fc8: 0xf149ef73
    823: 12989921: Illegal instruction (hart 0) at PC 0x80007fc8: 0xf149ef73
    824: 12989941: Illegal instruction (hart 0) at PC 0x80007fc8: 0xf149ef73
    825: 12989961: Illegal instruction (hart 0) at PC 0x80007fc8: 0xf149ef73
    826: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 13048171: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 827: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 13049891: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80002500 , but the ISS retired: ffffffff80002580
    828: 
    829: 
    830: --- RISC-V UVM TEST FAILED ---
    831: 
--------------------------------------------


riscv_mem_intg_error_test.10351
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.10351/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 11959: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 11959: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 56599: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 94779: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 127899: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 8001b4f0 expected: 0
    119: 
    120: 
    121: --- RISC-V UVM TEST FAILED ---
    122: 
--------------------------------------------


riscv_mem_intg_error_test.10368
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.10368/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 11539: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 11539: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 75839: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 105679: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 133339: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x14 DUT: 80013e5c expected: 0
    119: 
    120: 
    121: --- RISC-V UVM TEST FAILED ---
    122: 
--------------------------------------------


riscv_mem_intg_error_test.10375
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.10375/trace_core_00000000.log
    114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 12391: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12391: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 36971: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 77871: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x9 DUT: 8001af88 expected: 0
    118: 
    119: 
    120: --- RISC-V UVM TEST FAILED ---
    121: 
--------------------------------------------


riscv_mem_intg_error_test.10376
-------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.10376/trace_core_00000000.log
    119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1838) @ 18408: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
    120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 18408: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(167) @ 38888: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 95168: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 8001e2f5 expected: 0
    123: 
    124: 
    125: --- RISC-V UVM TEST FAILED ---
    126: 
--------------------------------------------


riscv_pc_intg_test.10340
------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.10340/trace_core_00000000.log not found


riscv_pc_intg_test.10343
------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.10343/trace_core_00000000.log not found


riscv_pc_intg_test.10345
------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.10345/trace_core_00000000.log not found


riscv_pmp_full_random_test.10532
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    120: 53997: Illegal instruction (hart 0) at PC 0x800031f0: 0x3b069073
    121: 2500177: Illegal instruction (hart 0) at PC 0x8000359e: 0x3a0b6073
    122: 2500217: Illegal instruction (hart 0) at PC 0x8000359e: 0x3a0b6073
    123: 2516737: Illegal instruction (hart 0) at PC 0x800035ae: 0x3b069073
    124: 2516777: Illegal instruction (hart 0) at PC 0x800035ae: 0x3b069073
[E] 125: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2571147: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 23220000 with data 9b but data 0 was expected with byte mask 1
    126: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 800035c2
    127: 
    128: 
    129: --- RISC-V UVM TEST FAILED ---
--------------------------------------------


riscv_pmp_full_random_test.10809
--------------------------------
binary:          test.bin
rtl_log:         rtl_sim.log
rtl_trace:       trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log

[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
    107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
    108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
    109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
    110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
    111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.10809/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1010634: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 477a0000 with data 79 but data e1 was expected with byte mask 1
    113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80003306
    114: 
    115: 
    116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------