Ibex Regression Results
Date/Time run: Sunday 14 June 2026 05:42 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
8 |
10 |
80.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
1 |
15 |
6.7% |
| riscv_hint_instr_test |
10 |
10 |
100.0% |
| riscv_ebreak_test |
10 |
10 |
100.0% |
| riscv_debug_basic_test |
9 |
10 |
90.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
10 |
10 |
100.0% |
| riscv_debug_instr_test |
25 |
25 |
100.0% |
| riscv_debug_wfi_test |
10 |
10 |
100.0% |
| riscv_dret_test |
5 |
5 |
100.0% |
| riscv_debug_ebreak_test |
14 |
15 |
93.3% |
| riscv_debug_ebreakmu_test |
14 |
15 |
93.3% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
10 |
10 |
100.0% |
| riscv_debug_in_irq_test |
10 |
10 |
100.0% |
| riscv_assorted_traps_interrupts_debug_test |
1 |
10 |
10.0% |
| riscv_single_interrupt_test |
15 |
15 |
100.0% |
| riscv_multiple_interrupt_test |
10 |
10 |
100.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
15 |
15 |
100.0% |
| riscv_mem_intg_error_test |
47 |
50 |
94.0% |
| riscv_debug_single_step_test |
9 |
15 |
60.0% |
| riscv_reset_test |
15 |
15 |
100.0% |
| riscv_pc_intg_test |
12 |
15 |
80.0% |
| riscv_rf_intg_test |
100 |
100 |
100.0% |
| riscv_rf_addr_intg_test |
13 |
15 |
86.7% |
| riscv_ram_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
12 |
15 |
80.0% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
50 |
50 |
100.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
48 |
50 |
96.0% |
| riscv_pmp_full_random_test |
578 |
600 |
96.3% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
20 |
20 |
100.0% |
| riscv_epmp_rlb_test |
20 |
20 |
100.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| riscv_debug_triggers_test |
0 |
5 |
0.0% |
| Total |
1456 |
1530 |
95.2% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 89.3% |
94.0% |
89.2% |
95.1% |
90.6% |
93.7% |
100.0% |
98.7% |
Test Failure Details
riscv_rand_jump_test.15177
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.15177/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 68002014: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 68002014: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_rand_jump_test.15178
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.15178/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 69002011: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 69002011: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.15174
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
125: 37240: Illegal instruction (hart 0) at PC 0x80002d0a: 0x0000677a
126: 70280: Illegal instruction (hart 0) at PC 0x80002d78: 0x00002cf4
127: 70300: Illegal instruction (hart 0) at PC 0x80002d78: 0x00002cf4
128: 92220: Illegal instruction (hart 0) at PC 0x80002e3e: 0x00000000
129: 92240: Illegal instruction (hart 0) at PC 0x80002e3e: 0x00000000
[E] 130: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 92270: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002000 but the DUT didn't report one at PC 80002e3c
131:
132:
133: --- RISC-V UVM TEST FAILED ---
134:
--------------------------------------------
riscv_illegal_instr_test.15175
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
132: 89637: Illegal instruction (hart 0) at PC 0x8000360c: 0x5c7d5e73
133: 110677: Illegal instruction (hart 0) at PC 0x800036ba: 0x02bd8ebb
134: 110697: Illegal instruction (hart 0) at PC 0x800036ba: 0x02bd8ebb
135: 137357: Illegal instruction (hart 0) at PC 0x800036e0: 0x00000000
136: 137377: Illegal instruction (hart 0) at PC 0x800036e0: 0x00000000
[E] 137: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 137407: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800036de
138:
139:
140: --- RISC-V UVM TEST FAILED ---
141:
--------------------------------------------
riscv_illegal_instr_test.15176
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
393: 2463394: Illegal instruction (hart 0) at PC 0x80008b30: 0xb28b1f2f
394: 2512714: Illegal instruction (hart 0) at PC 0x80008d22: 0x0181913b
395: 2512734: Illegal instruction (hart 0) at PC 0x80008d22: 0x0181913b
396: 2570874: Illegal instruction (hart 0) at PC 0x8000901e: 0x00000000
397: 2570894: Illegal instruction (hart 0) at PC 0x8000901e: 0x00000000
[E] 398: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2570924: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000901c
399:
400:
401: --- RISC-V UVM TEST FAILED ---
402:
--------------------------------------------
riscv_illegal_instr_test.15177
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
177: 609804: Illegal instruction (hart 0) at PC 0x80004c86: 0x00000000
178: 609804: Illegal instruction (hart 0) at PC 0x80004c86: 0x00000000
179: 609824: Illegal instruction (hart 0) at PC 0x80004c86: 0x00000000
180: 609824: Illegal instruction (hart 0) at PC 0x80004c86: 0x00000000
181: 609844: Illegal instruction (hart 0) at PC 0x80004c86: 0x00000000
[E] 182: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 609874: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80004c84
183:
184:
185: --- RISC-V UVM TEST FAILED ---
186:
--------------------------------------------
riscv_illegal_instr_test.15178
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
163: 214461: Illegal instruction (hart 0) at PC 0x80003838: 0x00007750
164: 257661: Illegal instruction (hart 0) at PC 0x80003a14: 0x0000a7e0
165: 257681: Illegal instruction (hart 0) at PC 0x80003a14: 0x0000a7e0
166: 280661: Illegal instruction (hart 0) at PC 0x80003af4: 0x00000000
167: 280681: Illegal instruction (hart 0) at PC 0x80003af4: 0x00000000
[E] 168: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 280711: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003af2
169:
170:
171: --- RISC-V UVM TEST FAILED ---
172:
--------------------------------------------
riscv_illegal_instr_test.15179
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
120: 175898: Illegal instruction (hart 0) at PC 0x80009d6c: 0x0000b6c0
121: 209438: Illegal instruction (hart 0) at PC 0x80009e34: 0x01a4f7bb
122: 209458: Illegal instruction (hart 0) at PC 0x80009e34: 0x01a4f7bb
123: 231838: Illegal instruction (hart 0) at PC 0x80009e92: 0x00000000
124: xmsim: *E,ASRTST (./tb/core_ibex_tb_top.sv,194): (time 231848 NS) Assertion core_ibex_tb_top.NoAlertsTriggered has failed
[E] 125: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(194) @ 231848: reporter [ASSERT FAILED] NoAlertsTriggered
126:
127: --- RISC-V UVM TEST FAILED ---
128:
129: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 231848: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.15180
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
165: 467754: Illegal instruction (hart 0) at PC 0x80004174: 0x414e013b
166: 467754: Illegal instruction (hart 0) at PC 0x80004174: 0x414e013b
167: 467774: Illegal instruction (hart 0) at PC 0x80004174: 0x414e013b
168: 485334: Illegal instruction (hart 0) at PC 0x800041be: 0x00000000
169: 485354: Illegal instruction (hart 0) at PC 0x800041be: 0x00000000
[E] 170: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 485364: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800041bc
171:
172:
173: --- RISC-V UVM TEST FAILED ---
174:
--------------------------------------------
riscv_illegal_instr_test.15182
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
139: 191161: Illegal instruction (hart 0) at PC 0x8000b720: 0x00000000
140: 191161: Illegal instruction (hart 0) at PC 0x8000b720: 0x00000000
141: 191181: Illegal instruction (hart 0) at PC 0x8000b720: 0x00000000
142: 191181: Illegal instruction (hart 0) at PC 0x8000b720: 0x00000000
143: 191201: Illegal instruction (hart 0) at PC 0x8000b720: 0x00000000
[E] 144: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 191231: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 8000b71e
145:
146:
147: --- RISC-V UVM TEST FAILED ---
148:
--------------------------------------------
riscv_illegal_instr_test.15183
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
245: 855238: Illegal instruction (hart 0) at PC 0x80007c00: 0x00006101
246: 869278: Illegal instruction (hart 0) at PC 0x80007c32: 0xd04cc1f3
247: 869298: Illegal instruction (hart 0) at PC 0x80007c32: 0xd04cc1f3
248: 903978: Illegal instruction (hart 0) at PC 0x80007ce0: 0x00000000
249: 903998: Illegal instruction (hart 0) at PC 0x80007ce0: 0x00000000
[E] 250: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 904028: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80007cde
251:
252:
253: --- RISC-V UVM TEST FAILED ---
254:
--------------------------------------------
riscv_illegal_instr_test.15184
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
251: 867115: Illegal instruction (hart 0) at PC 0x80004dec: 0x000074d2
252: 900815: Illegal instruction (hart 0) at PC 0x80004f46: 0x00006f81
253: 900835: Illegal instruction (hart 0) at PC 0x80004f46: 0x00006f81
254: 934775: Illegal instruction (hart 0) at PC 0x80004fb8: 0x00000000
255: 934795: Illegal instruction (hart 0) at PC 0x80004fb8: 0x00000000
[E] 256: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 934825: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80004fb6
257:
258:
259: --- RISC-V UVM TEST FAILED ---
260:
--------------------------------------------
riscv_illegal_instr_test.15185
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
217: 902052: Illegal instruction (hart 0) at PC 0x80009120: 0xfd0670d3
218: 902052: Illegal instruction (hart 0) at PC 0x80009120: 0xfd0670d3
219: 902072: Illegal instruction (hart 0) at PC 0x80009120: 0xfd0670d3
220: 931432: Illegal instruction (hart 0) at PC 0x80009186: 0x00000000
221: 931452: Illegal instruction (hart 0) at PC 0x80009186: 0x00000000
[E] 222: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 931482: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80009184
223:
224:
225: --- RISC-V UVM TEST FAILED ---
226:
--------------------------------------------
riscv_illegal_instr_test.15186
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: 58529: Illegal instruction (hart 0) at PC 0x80003610: 0x00002022
108: 98329: Illegal instruction (hart 0) at PC 0x80003758: 0xb5ee2cf3
109: 98349: Illegal instruction (hart 0) at PC 0x80003758: 0xb5ee2cf3
110: 129209: Illegal instruction (hart 0) at PC 0x80003a0e: 0x00000000
111: xmsim: *E,ASRTST (./tb/core_ibex_tb_top.sv,194): (time 129219 NS) Assertion core_ibex_tb_top.NoAlertsTriggered has failed
[E] 112: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(194) @ 129219: reporter [ASSERT FAILED] NoAlertsTriggered
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 129219: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.15187
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
624: 1837819: Illegal instruction (hart 0) at PC 0x8000ad5a: 0x7c53d71f
625: 1933059: Illegal instruction (hart 0) at PC 0x8000b242: 0x0000f15a
626: 1933079: Illegal instruction (hart 0) at PC 0x8000b242: 0x0000f15a
627: 1971479: Illegal instruction (hart 0) at PC 0x8000b2e4: 0x00000000
628: 1971499: Illegal instruction (hart 0) at PC 0x8000b2e4: 0x00000000
[E] 629: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1971529: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000b2e2
630:
631:
632: --- RISC-V UVM TEST FAILED ---
633:
--------------------------------------------
riscv_illegal_instr_test.15188
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: 227336: Illegal instruction (hart 0) at PC 0x8000bec2: 0x417cf03b
118: 250196: Illegal instruction (hart 0) at PC 0x8000bece: 0x18c504f3
119: 250216: Illegal instruction (hart 0) at PC 0x8000bece: 0x18c504f3
120: 270936: Illegal instruction (hart 0) at PC 0x8000bfa8: 0x00000000
121: 270956: Illegal instruction (hart 0) at PC 0x8000bfa8: 0x00000000
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 270986: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000bfa6
123:
124:
125: --- RISC-V UVM TEST FAILED ---
126:
--------------------------------------------
riscv_debug_basic_test.15175
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_basic_test.15175/trace_core_00000000.log
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 33067: reporter@@debug_seq_stress_h [debug_seq_stress_h] Starting sequence...
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 10847567: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : 80000000 , but the ISS retired: 800055f6
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_debug_triggers_test.15174
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
161: 884440: Illegal instruction (hart 0) at PC 0x80003542: 0x00000000
162: 884440: Illegal instruction (hart 0) at PC 0x80003542: 0x00000000
163: 884460: Illegal instruction (hart 0) at PC 0x80003542: 0x00000000
164: 884460: Illegal instruction (hart 0) at PC 0x80003542: 0x00000000
165: 884480: Illegal instruction (hart 0) at PC 0x80003542: 0x00000000
[E] 166: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 884510: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002000 but the DUT didn't report one at PC 80003540
167:
168:
169: --- RISC-V UVM TEST FAILED ---
170:
--------------------------------------------
riscv_debug_triggers_test.15175
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
216: 2915917: Illegal instruction (hart 0) at PC 0x80005e8a: 0x3d2d383f
217: 2945357: Illegal instruction (hart 0) at PC 0x80005f34: 0x4204bd03
218: 2945377: Illegal instruction (hart 0) at PC 0x80005f34: 0x4204bd03
219: 3002557: Illegal instruction (hart 0) at PC 0x800060f6: 0x00000000
220: 3002577: Illegal instruction (hart 0) at PC 0x800060f6: 0x00000000
[E] 221: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 3002607: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800060f4
222:
223:
224: --- RISC-V UVM TEST FAILED ---
225:
--------------------------------------------
riscv_debug_triggers_test.15176
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
206: 2487234: Illegal instruction (hart 0) at PC 0x80005ba0: 0x00002e72
207: 2510854: Illegal instruction (hart 0) at PC 0x80005c6a: 0x01fc27f3
208: 2510874: Illegal instruction (hart 0) at PC 0x80005c6a: 0x01fc27f3
209: 2548234: Illegal instruction (hart 0) at PC 0x80005d6a: 0x00000000
210: 2548254: Illegal instruction (hart 0) at PC 0x80005d6a: 0x00000000
[E] 211: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2548264: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80005d68
212:
213:
214: --- RISC-V UVM TEST FAILED ---
215:
--------------------------------------------
riscv_debug_triggers_test.15177
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
209: 2516404: Illegal instruction (hart 0) at PC 0x80005980: 0x0000506a
210: 2561684: Illegal instruction (hart 0) at PC 0x800059b6: 0x7cfaec27
211: 2561704: Illegal instruction (hart 0) at PC 0x800059b6: 0x7cfaec27
212: 2574584: Illegal instruction (hart 0) at PC 0x800059e4: 0xca8a8d5b
213: 2574604: Illegal instruction (hart 0) at PC 0x800059e4: 0xca8a8d5b
[E] 214: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2614214: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80005a1e
215:
216:
217: --- RISC-V UVM TEST FAILED ---
218:
--------------------------------------------
riscv_debug_triggers_test.15178
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_triggers_test.15178/trace_core_00000000.log
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 28091: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 29591: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 114: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 147191: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 800033b8
115:
116:
117: --- RISC-V UVM TEST FAILED ---
118:
--------------------------------------------
riscv_debug_ebreak_test.15187
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
3405: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 67878129: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
3406: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 67929989: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
3407: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 67931489: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
3408: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 67968909: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
3409: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 67970409: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 3410: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 68002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
3411:
3412: --- RISC-V UVM TEST FAILED ---
3413:
3414: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 68002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.15187
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.15187/trace_core_00000000.log
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 33329: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 34849: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 69002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 69002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15174
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
152: 144940: Illegal instruction (hart 0) at PC 0x8000c47c: 0x463300df
153: 144940: Illegal instruction (hart 0) at PC 0x8000c47c: 0x463300df
154: 144960: Illegal instruction (hart 0) at PC 0x8000c47c: 0x463300df
155: 144960: Illegal instruction (hart 0) at PC 0x8000c47c: 0x463300df
156: 144980: Illegal instruction (hart 0) at PC 0x8000c47c: 0x463300df
[E] 157: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 145010: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000c478
158:
159:
160: --- RISC-V UVM TEST FAILED ---
161:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15175
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
2230: 37827957: Illegal instruction (hart 0) at PC 0xda4a843a: 0x00000000
2231: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
2232: IRQs last cycle: 08000, IRQs this cycle: 00000
2233: 37846557: Illegal instruction (hart 0) at PC 0xda4a843e: 0x00000000
2234: 37846577: Illegal instruction (hart 0) at PC 0xda4a843e: 0x00000000
[E] 2235: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 37846627: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch PC mismatch, DUT retired : da4a843e , but the ISS retired: 8000252c
2236:
2237:
2238: --- RISC-V UVM TEST FAILED ---
2239:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15176
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
192: 751154: Illegal instruction (hart 0) at PC 0x8000899e: 0x00000000
193: 751154: Illegal instruction (hart 0) at PC 0x8000899e: 0x00000000
194: 751174: Illegal instruction (hart 0) at PC 0x8000899e: 0x00000000
195: 751174: Illegal instruction (hart 0) at PC 0x8000899e: 0x00000000
196: 751194: Illegal instruction (hart 0) at PC 0x8000899e: 0x00000000
[E] 197: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 751224: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000899c
198:
199:
200: --- RISC-V UVM TEST FAILED ---
201:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15177
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
134: 437644: Illegal instruction (hart 0) at PC 0x80027b92: 0x0000f900
135: 437664: Illegal instruction (hart 0) at PC 0x80027b92: 0x0000f900
136: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 445514: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 2/5
137: 476084: Illegal instruction (hart 0) at PC 0x80027b0e: 0x0000f900
138: 476104: Illegal instruction (hart 0) at PC 0x80027b0e: 0x0000f900
[E] 139: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 479494: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800020be
140:
141:
142: --- RISC-V UVM TEST FAILED ---
143:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15178
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
180: 1395721: Illegal instruction (hart 0) at PC 0x000003ba: 0x00000000
181: 1482701: Illegal instruction (hart 0) at PC 0x8000c11e: 0x00000000
182: 1482721: Illegal instruction (hart 0) at PC 0x8000c11e: 0x00000000
183: 1537001: Illegal instruction (hart 0) at PC 0x8000bd2c: 0xd5cb20ab
184: 1537021: Illegal instruction (hart 0) at PC 0x8000bd2c: 0xd5cb20ab
[E] 185: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1539611: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002216
186:
187:
188: --- RISC-V UVM TEST FAILED ---
189:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15179
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
177: 1004718: Illegal instruction (hart 0) at PC 0x800096fe: 0x5caad573
178: 1089358: Illegal instruction (hart 0) at PC 0x80009dba: 0x19723b83
179: 1089378: Illegal instruction (hart 0) at PC 0x80009dba: 0x19723b83
180: 1185738: Illegal instruction (hart 0) at PC 0x80009e90: 0x0000391e
181: 1185758: Illegal instruction (hart 0) at PC 0x80009e90: 0x0000391e
[E] 182: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1247208: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000a07a
183:
184:
185: --- RISC-V UVM TEST FAILED ---
186:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15180
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(75) @ 36924: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Number of stimulus iterations = 7
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 36924: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 0/7
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 36924: uvm_test_top.env.irq_agent.sequencer@@irq_new_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_new_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
115: 51174: Illegal instruction (hart 0) at PC 0x80003584: 0x00000000
116: 51194: Illegal instruction (hart 0) at PC 0x80003584: 0x00000000
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 51224: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003582
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15181
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
125: 332991: Illegal instruction (hart 0) at PC 0x80003b80: 0xf84ebdf3
126: 333011: Illegal instruction (hart 0) at PC 0x80003b80: 0xf84ebdf3
127: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 464741: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 2/10
128: 553511: Illegal instruction (hart 0) at PC 0x80003dc6: 0x00000000
129: 553531: Illegal instruction (hart 0) at PC 0x80003dc6: 0x00000000
[E] 130: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 553561: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003dc4
131:
132:
133: --- RISC-V UVM TEST FAILED ---
134:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.15183
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
149: 912178: Illegal instruction (hart 0) at PC 0x80005f5c: 0x00000000
150: 912178: Illegal instruction (hart 0) at PC 0x80005f5c: 0x00000000
151: 912198: Illegal instruction (hart 0) at PC 0x80005f5c: 0x00000000
152: 912198: Illegal instruction (hart 0) at PC 0x80005f5c: 0x00000000
153: 912218: Illegal instruction (hart 0) at PC 0x80005f5c: 0x00000000
[E] 154: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 912248: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 80005f5a
155:
156:
157: --- RISC-V UVM TEST FAILED ---
158:
--------------------------------------------
riscv_mem_intg_error_test.15178
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13211: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 13211: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 99411: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 159171: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 222371: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 272431: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x14 DUT: 8001e6a8 expected: 0
121:
122:
123: --- RISC-V UVM TEST FAILED ---
124:
--------------------------------------------
riscv_mem_intg_error_test.15190
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 20180: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 20180: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 108800: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 196460: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 217880: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 295680: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x29 DUT: 80028e40 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.15202
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
118: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.15202/trace_core_00000000.log
119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1871) @ 33982: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 33982: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 60802: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 101522: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x29 DUT: 80020e7a expected: 0
123:
124:
125: --- RISC-V UVM TEST FAILED ---
126:
--------------------------------------------
riscv_debug_single_step_test.15174
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
623: 5266360: Illegal instruction (hart 0) at PC 0x8000b47a: 0xe09e1d73
624: 5283140: Illegal instruction (hart 0) at PC 0x8000b47a: 0xe09e1d73
625: 5283160: Illegal instruction (hart 0) at PC 0x8000b47a: 0xe09e1d73
626: 5296080: Illegal instruction (hart 0) at PC 0x8000b47a: 0xe09e1d73
627: 5296100: Illegal instruction (hart 0) at PC 0x8000b47a: 0xe09e1d73
[E] 628: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 5299430: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000000 but the DUT didn't report one at PC 800020dc
629:
630:
631: --- RISC-V UVM TEST FAILED ---
632:
--------------------------------------------
riscv_debug_single_step_test.15180
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
136: 2432534: Illegal instruction (hart 0) at PC 0x80003b84: 0x7b200073
137: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 2472764: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
138: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 2474264: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
139: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 2976124: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
140: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 2977624: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 141: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 3008304: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000000 but the DUT didn't report one at PC 80003bfe
142:
143:
144: --- RISC-V UVM TEST FAILED ---
145:
--------------------------------------------
riscv_debug_single_step_test.15182
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
119: 543241: Illegal instruction (hart 0) at PC 0x8000349a: 0x7b200073
120: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 568291: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
121: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 569791: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
122: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 1526711: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
123: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 1528211: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1547631: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000bb34
125:
126:
127: --- RISC-V UVM TEST FAILED ---
128:
--------------------------------------------
riscv_debug_single_step_test.15184
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
123: 1169675: Illegal instruction (hart 0) at PC 0x80025e82: 0x00002172
124: 1183675: Illegal instruction (hart 0) at PC 0x80025e86: 0x0000ec74
125: 1183695: Illegal instruction (hart 0) at PC 0x80025e86: 0x0000ec74
126: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 1192905: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
127: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 1194405: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 128: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1295925: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80000008 but the DUT didn't report one at PC 8000bd3e
129:
130:
131: --- RISC-V UVM TEST FAILED ---
132:
--------------------------------------------
riscv_debug_single_step_test.15185
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
153: 1603972: Illegal instruction (hart 0) at PC 0x7596c97a: 0x00000000
154: 1616932: Illegal instruction (hart 0) at PC 0x7596c97e: 0x00000000
155: 1616952: Illegal instruction (hart 0) at PC 0x7596c97e: 0x00000000
156: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 1625082: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
157: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 1626582: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 158: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 2047262: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002800 but the DUT didn't report one at PC 8000291c
159:
160:
161: --- RISC-V UVM TEST FAILED ---
162:
--------------------------------------------
riscv_debug_single_step_test.15186
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
208: 10075289: Illegal instruction (hart 0) at PC 0x4000011e: 0x00000000
209: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(46) @ 10077119: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
210: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(58) @ 10078639: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
211: 10427049: Illegal instruction (hart 0) at PC 0x40000122: 0x00000000
212: 10427069: Illegal instruction (hart 0) at PC 0x40000122: 0x00000000
[E] 213: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 10427119: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x8, but a write was expected
214:
215:
216: --- RISC-V UVM TEST FAILED ---
217:
--------------------------------------------
riscv_pc_intg_test.15180
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.15180/trace_core_00000000.log not found
riscv_pc_intg_test.15184
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.15184/trace_core_00000000.log not found
riscv_pc_intg_test.15186
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.15186/trace_core_00000000.log not found
riscv_rf_addr_intg_test.15175
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_rf_addr_intg_test.15175/trace_core_00000000.log
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(266) @ 154617: uvm_test_top [uvm_test_top] Reading value of core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i.raddr_b_i
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(268) @ 154617: uvm_test_top [uvm_test_top] Read 0000000d
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(278) @ 154617: uvm_test_top [uvm_test_top] Forcing core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i.raddr_b_i to value 'hf
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 154617: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(294) @ 154637: reporter [uvm_test_top] Check failed (|ecc_err) ECC alert did not fire!
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 154637: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_rf_addr_intg_test.15179
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: 71658: Illegal instruction (hart 0) at PC 0x80005902: 0xf13b1c73
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(266) @ 103118: uvm_test_top [uvm_test_top] Reading value of core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_b_i
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(268) @ 103118: uvm_test_top [uvm_test_top] Read 00000000
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(278) @ 103118: uvm_test_top [uvm_test_top] Forcing core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.gen_shadow_regfile_ff.register_file_shadow_i.raddr_b_i to value 'h2
111: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 103118: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(294) @ 103119: reporter [uvm_test_top] Check failed (|ecc_err) ECC alert did not fire!
113:
114: --- RISC-V UVM TEST FAILED ---
115:
116: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 103119: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.15180
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 29114: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 29114: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 29114: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ca81b98107c007301fc
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 29114: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ca81b98107c007321fc
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 29114: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 29134: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 29134: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.15183
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 29758: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 29758: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 29758: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700099810420073c30c
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 29758: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000701099810420073c30c
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 29758: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 29778: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 29778: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_icache_intg_test.15184
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(554) @ 45115: uvm_test_top [uvm_test_top] The following I$ data ways are valid and used in this clock cycle: '{0}
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(558) @ 45115: uvm_test_top [uvm_test_top] Corrupting data way 0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(563) @ 45115: uvm_test_top [uvm_test_top] Original data_rdata of way 0: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007000998100b00730144
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(569) @ 45115: uvm_test_top [uvm_test_top] Corrupting data_rdata: 'hx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007000998100b00770144
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(195) @ 45115: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(590) @ 45135: reporter [uvm_test_top] Check failed alert_minor == exp_alert_minor (1 [0x1] vs 0 [0x0])
118:
119: --- RISC-V UVM TEST FAILED ---
120:
121: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 45135: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.15184
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.15184/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 11002025: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002025: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.15207
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.15207/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(381) @ 11002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 11002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.15196
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
239: 662324: Illegal instruction (hart 0) at PC 0x8000a032: 0x3a0b6073
240: 662324: Illegal instruction (hart 0) at PC 0x8000a032: 0x3a0b6073
241: 662344: Illegal instruction (hart 0) at PC 0x8000a032: 0x3a0b6073
242: 673344: Illegal instruction (hart 0) at PC 0x8000a044: 0x3b039073
243: 673364: Illegal instruction (hart 0) at PC 0x8000a044: 0x3b039073
[E] 244: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 735834: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 8000a402
245:
246:
247: --- RISC-V UVM TEST FAILED ---
248:
--------------------------------------------
riscv_pmp_full_random_test.15209
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15209/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 86074: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800038c6
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15247
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15247/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 729922: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data d000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80006f2e
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15303
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15303/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 407613: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address fffffffc but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15337
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15337/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 255240: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 57000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80005f0a
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15338
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15338/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 26017: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 53000000 but data 0 was expected with byte mask 8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15374
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15374/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 235678: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 1d940000 with data f but data d was expected with byte mask 1
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80005f14
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15393
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15393/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 184372: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 8001c5d2
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15413
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
145: 1280293: Illegal instruction (hart 0) at PC 0x80003888: 0x3b0c9073
146: 1298913: Illegal instruction (hart 0) at PC 0x8000390a: 0x3a08e073
147: 1298933: Illegal instruction (hart 0) at PC 0x8000390a: 0x3a08e073
148: 1321593: Illegal instruction (hart 0) at PC 0x8000391c: 0x3b0c9073
149: 1321613: Illegal instruction (hart 0) at PC 0x8000391c: 0x3b0c9073
[E] 150: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1336923: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 280000 but data 0 was expected with byte mask 4
151: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003922
152:
153:
154: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15420
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15420/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1676674: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80007ad2
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15452
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15452/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 21467: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 57000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 800033e8
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15454
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(207) @ 2021: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15454/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 45301: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 7b000000 but data 0 was expected with byte mask 8
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_pmp_full_random_test.15504
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15504/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 25538: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 720000 but data 0 was expected with byte mask 4
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800034be
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15511
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
201: 460873: Illegal instruction (hart 0) at PC 0x80003b62: 0x3b091073
202: 474373: Illegal instruction (hart 0) at PC 0x80003b66: 0x3a0ae073
203: 474393: Illegal instruction (hart 0) at PC 0x80003b66: 0x3a0ae073
204: 490153: Illegal instruction (hart 0) at PC 0x80003b78: 0x3b091073
205: 490173: Illegal instruction (hart 0) at PC 0x80003b78: 0x3b091073
[E] 206: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 527863: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data 630000 but data 0 was expected with byte mask 4
207: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80003ce4
208:
209:
210: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15523
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15523/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 351152: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data f1000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 800047ae
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15550
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15550/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1534175: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ec000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000faa0
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15560
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(207) @ 2010: reporter [core_ibex_tb_top.g_lockstep_assert_ctrl.unmblk1] Disabling assertions: core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.NoMemResponseWithoutPendingAccess
113: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15560/trace_core_00000000.log
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 86490: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003d12
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_pmp_full_random_test.15600
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15600/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 193652: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ed0000 but data 0 was expected with byte mask 4
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003fb4
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15680
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15680/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 314735: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x16 DUT: 0 expected: ffffffff
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15685
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2013: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2013: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2013: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15685/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 39813: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ea000000 but data 0 was expected with byte mask 8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.15754
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(370) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(44) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.15754/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 49964: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data fe000000 but data 0 was expected with byte mask 8
113: Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 8000369a
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.15768
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
119: 347250: Illegal instruction (hart 0) at PC 0x80003d4c: 0x3b071073
120: 365970: Illegal instruction (hart 0) at PC 0x80003d50: 0x3a086073
121: 365990: Illegal instruction (hart 0) at PC 0x80003d50: 0x3a086073
122: 380950: Illegal instruction (hart 0) at PC 0x80003d60: 0x3b071073
123: 380970: Illegal instruction (hart 0) at PC 0x80003d60: 0x3b071073
[E] 124: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(172) @ 1648360: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address fffffffc with data ba000000 but data 0 was expected with byte mask 8
125: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80004002
126:
127:
128: --- RISC-V UVM TEST FAILED ---
--------------------------------------------