Ibex Regression Results
Date/Time run: Thursday 06 June 2024 04:06 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
9 |
10 |
90.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
14 |
15 |
93.3% |
| riscv_hint_instr_test |
10 |
10 |
100.0% |
| riscv_ebreak_test |
10 |
10 |
100.0% |
| riscv_debug_basic_test |
9 |
10 |
90.0% |
| riscv_debug_triggers_test |
5 |
5 |
100.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
8 |
10 |
80.0% |
| riscv_debug_instr_test |
23 |
25 |
92.0% |
| riscv_debug_wfi_test |
10 |
10 |
100.0% |
| riscv_dret_test |
3 |
5 |
60.0% |
| riscv_debug_ebreak_test |
14 |
15 |
93.3% |
| riscv_debug_ebreakmu_test |
13 |
15 |
86.7% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
9 |
10 |
90.0% |
| riscv_debug_in_irq_test |
9 |
10 |
90.0% |
| riscv_assorted_traps_interrupts_debug_test |
4 |
10 |
40.0% |
| riscv_single_interrupt_test |
13 |
15 |
86.7% |
| riscv_multiple_interrupt_test |
9 |
10 |
90.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
12 |
15 |
80.0% |
| riscv_mem_intg_error_test |
43 |
50 |
86.0% |
| riscv_debug_single_step_test |
15 |
15 |
100.0% |
| riscv_reset_test |
13 |
15 |
86.7% |
| riscv_pc_intg_test |
13 |
15 |
86.7% |
| riscv_rf_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
15 |
15 |
100.0% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
49 |
50 |
98.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
44 |
50 |
88.0% |
| riscv_pmp_full_random_test |
542 |
600 |
90.3% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
19 |
20 |
95.0% |
| riscv_epmp_rlb_test |
20 |
20 |
100.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| Total |
1312 |
1415 |
92.7% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 93.7% |
95.7% |
90.3% |
95.8% |
90.5% |
97.3% |
100.0% |
98.1% |
Test Failure Details
riscv_rand_jump_test.27384
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2036: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2036: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2036: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2036: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_rand_jump_test.27384/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 38002036: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 38002036: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_illegal_instr_test.27384
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4585: 36944166: Illegal instruction (hart 0) at PC 0x8000bb62: 0xceaad5c3
4586: 36967526: Illegal instruction (hart 0) at PC 0x8000bb62: 0xceaad5c3
4587: 36967566: Illegal instruction (hart 0) at PC 0x8000bb62: 0xceaad5c3
4588: 36994966: Illegal instruction (hart 0) at PC 0x8000bb62: 0xceaad5c3
4589: 36995006: Illegal instruction (hart 0) at PC 0x8000bb62: 0xceaad5c3
[E] 4590: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002036: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4591:
4592: --- RISC-V UVM TEST FAILED ---
4593:
4594: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002036: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_basic_test.27382
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
riscv_debug_branch_jump_test.27379
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_branch_jump_test.27379/trace_core_00000000.log
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 34639: reporter@@debug_seq_stress_h [debug_seq_stress_h] Starting sequence...
[E] 113: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 38002019: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
114:
115: --- RISC-V UVM TEST FAILED ---
116:
117: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 38002019: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_branch_jump_test.27385
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_branch_jump_test.27385/trace_core_00000000.log
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 32106: reporter@@debug_seq_stress_h [debug_seq_stress_h] Starting sequence...
[E] 113: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 38002026: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
114:
115: --- RISC-V UVM TEST FAILED ---
116:
117: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 38002026: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_instr_test.27400
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36861700: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36920240: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36921740: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36978420: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36979900: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1111:
1112: --- RISC-V UVM TEST FAILED ---
1113:
1114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_instr_test.27401
----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1197: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35751116: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1198: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 35802136: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1199: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35803636: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1200: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 35973756: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1201: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35975256: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1202: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002016: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1203:
1204: --- RISC-V UVM TEST FAILED ---
1205:
1206: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002016: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.27380
---------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.27380/trace_core_00000000.log
108: 28959: Illegal instruction (hart 0) at PC 0x80003792: 0x7b200073
109: 28999: Illegal instruction (hart 0) at PC 0x80003792: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 52749: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(843) @ 59889: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 59889: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.27381
---------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.27381/trace_core_00000000.log
108: 80916: Illegal instruction (hart 0) at PC 0x80003912: 0x7b200073
109: 80956: Illegal instruction (hart 0) at PC 0x80003912: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 95466: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(843) @ 103186: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 103186: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreak_test.27386
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
1957: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37892283: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1958: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 37929723: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1959: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37931223: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
1960: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 37962783: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
1961: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 37964283: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
[E] 1962: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 38002023: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
1963:
1964: --- RISC-V UVM TEST FAILED ---
1965:
1966: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 38002023: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.27380
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.27380/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1551) @ 28529: uvm_test_top [uvm_test_top] EBreak seen whilst doing initial debug initialization, KNOWN FAILURE SEE https://github.com/lowRISC/ibex/issues/1313
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 28529: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_ebreakmu_test.27384
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2036: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 1800s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2036: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2036: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2036: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_ebreakmu_test.27384/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1551) @ 36176: uvm_test_top [uvm_test_top] EBreak seen whilst doing initial debug initialization, KNOWN FAILURE SEE https://github.com/lowRISC/ibex/issues/1313
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36176: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_irq_in_debug_mode_test.27386
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
6115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35986013: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Exiting sequence
6116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 35986043: uvm_test_top [uvm_test_top] irq: 0x16120000
6117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 35986043: uvm_test_top [uvm_test_top] irq_id: 0x11
6118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 35988003: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
6119: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 35988013: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 6120: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002023: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
6121:
6122: --- RISC-V UVM TEST FAILED ---
6123:
6124: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002023: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_in_irq_test.27386
-----------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
4447: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(778) @ 36943003: uvm_test_top [uvm_test_top] mcause: 0x8000001f
4448: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36943843: reporter@@debug_seq_single_h [debug_seq_single_h] Starting sequence...
4449: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36945323: reporter@@debug_seq_single_h [debug_seq_single_h] Exiting sequence
4450: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36981963: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Starting sequence...
4451: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36981973: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
[E] 4452: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002023: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
4453:
4454: --- RISC-V UVM TEST FAILED ---
4455:
4456: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002023: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27380
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
210: 3056099: Illegal instruction (hart 0) at PC 0x00000000: 0x00010413
211: 3142999: Illegal instruction (hart 0) at PC 0x00000004: 0x00010413
212: 3143039: Illegal instruction (hart 0) at PC 0x00000004: 0x00010413
213: 3161099: Illegal instruction (hart 0) at PC 0x00000008: 0x00010413
214: 3161139: Illegal instruction (hart 0) at PC 0x00000008: 0x00010413
[E] 215: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 3161169: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x4, but a write was expected
216:
217:
218: --- RISC-V UVM TEST FAILED ---
219:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27382
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
123: 237473: Illegal instruction (hart 0) at PC 0x8000c7fc: 0x00007016
124: 237513: Illegal instruction (hart 0) at PC 0x8000c7fc: 0x00007016
125: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 241863: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 1/3
126: 259853: Illegal instruction (hart 0) at PC 0x8000c7fc: 0x00007016
127: 259893: Illegal instruction (hart 0) at PC 0x8000c7fc: 0x00007016
[E] 128: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 375623: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x9 DUT: 0 expected: 1000000
129:
130:
131: --- RISC-V UVM TEST FAILED ---
132:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27383
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
474: 7194629: Illegal instruction (hart 0) at PC 0x000002a8: 0x00010413
475: 7264669: Illegal instruction (hart 0) at PC 0x000002ac: 0x00010413
476: 7264709: Illegal instruction (hart 0) at PC 0x000002ac: 0x00010413
477: 7368729: Illegal instruction (hart 0) at PC 0x000002b0: 0x00010413
478: 7368769: Illegal instruction (hart 0) at PC 0x000002b0: 0x00010413
[E] 479: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 7410359: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x24 DUT: 0 expected: 4000000
480:
481:
482: --- RISC-V UVM TEST FAILED ---
483:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27384
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
157: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(77) @ 1042076: uvm_test_top.env.irq_agent.sequencer@@debug_new_seq_h [uvm_test_top.env.irq_agent.sequencer.debug_new_seq_h] Running 5/5
158: 1059886: Illegal instruction (hart 0) at PC 0x8000c846: 0x0ec12003
159: 1059926: Illegal instruction (hart 0) at PC 0x8000c846: 0x0ec12003
160: 1348526: Illegal instruction (hart 0) at PC 0x0000001c: 0x00010413
161: 1348566: Illegal instruction (hart 0) at PC 0x0000001c: 0x00010413
[E] 162: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1384456: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x12 DUT: 0 expected: 10000000
163:
164:
165: --- RISC-V UVM TEST FAILED ---
166:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27385
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
177: 1320736: Illegal instruction (hart 0) at PC 0x80009afa: 0x4023ddbb
178: 1573696: Illegal instruction (hart 0) at PC 0x8000a9a4: 0x00003548
179: 1573736: Illegal instruction (hart 0) at PC 0x8000a9a4: 0x00003548
180: 1712716: Illegal instruction (hart 0) at PC 0x8000b0ba: 0x1346421f
181: 1712756: Illegal instruction (hart 0) at PC 0x8000b0ba: 0x1346421f
[E] 182: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1759046: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x10 DUT: 0 expected: 80
183:
184:
185: --- RISC-V UVM TEST FAILED ---
186:
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.27386
------------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
602: 8402873: Illegal instruction (hart 0) at PC 0xfffffff2: 0x0800ffff
603: 8416353: Illegal instruction (hart 0) at PC 0xfffffff6: 0x00010413
604: 8416393: Illegal instruction (hart 0) at PC 0xfffffff6: 0x00010413
605: 8441373: Illegal instruction (hart 0) at PC 0xfffffffa: 0x00010413
606: 8441413: Illegal instruction (hart 0) at PC 0xfffffffa: 0x00010413
[E] 607: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 8441443: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch A load at address fffffffa was expected but there are no pending accesses
608:
609:
610: --- RISC-V UVM TEST FAILED ---
611:
--------------------------------------------
riscv_single_interrupt_test.27388
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
8467: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36958687: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Exiting sequence
8468: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 36971657: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Starting sequence...
8469: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(55) @ 36971667: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Exiting sequence
8470: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 36971697: uvm_test_top [uvm_test_top] irq: 0x10000000
8471: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 36971697: uvm_test_top [uvm_test_top] irq_id: 0x1c
[E] 8472: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 37002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
8473:
8474: --- RISC-V UVM TEST FAILED ---
8475:
8476: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 37002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_single_interrupt_test.27391
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
3573: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(283) @ 10763721: uvm_test_top [uvm_test_top] Test done due to RISCV-DV handshake (payload=TEST_PASS)
3574: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 10763721: uvm_test_top.env.irq_agent.sequencer@@irq_single_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_single_seq_h] Stopping sequence
3575: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 10763721: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Stopping sequence
3576: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 10763721: uvm_test_top [uvm_test_top] irq: 0x20000000
3577: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 10763721: uvm_test_top [uvm_test_top] irq_id: 0x1d
[E] 3578: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(418) @ 10808161: reporter [uvm_test_top] Check failed signature_data == core_status (8 [0x8] vs 6 [0x6]) Core did not jump to vectored interrupt handler
3579:
3580: --- RISC-V UVM TEST FAILED ---
3581:
3582: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 10808161: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_multiple_interrupt_test.27385
-----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
2380: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(627) @ 10036346: uvm_test_top [uvm_test_top] irq: 0x8ff0000
2381: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(630) @ 10036346: uvm_test_top [uvm_test_top] irq_id: 0x11
2382: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(283) @ 10036406: uvm_test_top [uvm_test_top] Test done due to RISCV-DV handshake (payload=TEST_PASS)
2383: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 10036406: uvm_test_top.env.irq_agent.sequencer@@irq_raise_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_raise_seq_h] Stopping sequence
2384: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(64) @ 10036406: uvm_test_top.env.irq_agent.sequencer@@irq_drop_seq_h [uvm_test_top.env.irq_agent.sequencer.irq_drop_seq_h] Stopping sequence
[E] 2385: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(418) @ 10078266: reporter [uvm_test_top] Check failed signature_data == core_status (8 [0x8] vs 6 [0x6]) Core did not jump to vectored interrupt handler
2386:
2387: --- RISC-V UVM TEST FAILED ---
2388:
2389: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 10078266: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_mem_error_test.27378
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
456: 5369072: Illegal instruction (hart 0) at PC 0x8000c324: 0xf13b9af3
457: 5369112: Illegal instruction (hart 0) at PC 0x8000c324: 0xf13b9af3
458: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 5393542: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
459: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 5469762: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
460: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 5470182 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.u_fcov_bind.uarch_cg_inst@11444_629.exception_stall_instr_cross).
[E] 461: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 5470222 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.u_fcov_bind.uarch_cg_inst@11461_1.exception_stall_instr_cross).
462: 5506972: Illegal instruction (hart 0) at PC 0x8000ca34: 0xf14b64f3
463: 5507012: Illegal instruction (hart 0) at PC 0x8000ca34: 0xf14b64f3
464: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 5535722: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
465: 5543912: Illegal instruction (hart 0) at PC 0x8000ccc8: 0xf1105e73
--------------------------------------------
riscv_mem_error_test.27379
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
377: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6684219: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
378: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6777119: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
379: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6813459: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
380: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6877579: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
381: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 6878959 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.u_fcov_bind.uarch_cg_inst@11444_629.exception_stall_instr_cross).
[E] 382: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 6878999 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.u_fcov_bind.uarch_cg_inst@11461_1.exception_stall_instr_cross).
383: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6898459: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
384: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6938619: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
385: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 6980739: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
386: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 7024099: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
--------------------------------------------
riscv_mem_error_test.27391
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
126: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 548141: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
127: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 603981: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
128: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 662561: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
129: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 755381: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
130: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 756681 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.u_fcov_bind.uarch_cg_inst@11444_629.exception_stall_instr_cross).
[E] 131: xmsim: *SE,EILLCT: (File: ./fcov/core_ibex_fcov_if.sv, Line: 718):(Time: 756721 NS + 4) Illegal cross tuple (<0, 1, InstrCategoryFetchError, IdStallTypeMem, 0, 0, 0>) occurred corresponding to illegal cross bin (mem_stall_illegal) of cross (core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_shadow_core.u_fcov_bind.uarch_cg_inst@11461_1.exception_stall_instr_cross).
132: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 784921: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
133: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 822361: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
134: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 898881: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
135: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 923101: reporter [core_ibex_tb_top.unmblk1] Enabling assertions: core_ibex_tb_top.NoAlertsTriggered
--------------------------------------------
riscv_mem_intg_error_test.27390
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.27390/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 31404: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 31404: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 31404: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 86164: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 116524: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x26 DUT: 8001365c expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.27397
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.27397/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 14116: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14116: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 35156: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 74536: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 78796: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x17 DUT: 8001f2f7 expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.27399
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2030: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.27399/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 14590: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14590: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 110490: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 157390: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x22 DUT: 80013243 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.27406
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 12674: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12674: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 12674: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 95234: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 119554: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 151754: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x10 DUT: 8002cca0 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.27413
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.27413/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 25386: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 25386: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 25386: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 72426: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x7 DUT: 80028e58 expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.27420
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.27420/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 14330: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 14330: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 42350: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 125870: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 164750: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x13 DUT: 80013c37 expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_mem_intg_error_test.27423
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1643) @ 12941: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12941: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 79041: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 97441: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(163) @ 136521: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 159381: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x17 DUT: 8001af6b expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_reset_test.27383
----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
223: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 33314999: uvm_test_top [uvm_test_top] Reset now inactive
224: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 33812788: uvm_test_top [uvm_test_top] Reset now active
225: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 33814779: uvm_test_top [uvm_test_top] Reset now inactive
226: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 34745328: uvm_test_top [uvm_test_top] Reset now active
227: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 34747319: uvm_test_top [uvm_test_top] Reset now inactive
[E] 228: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 35002019: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
229:
230: --- RISC-V UVM TEST FAILED ---
231:
232: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 35002019: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_reset_test.27388
----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
217: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 29640217: uvm_test_top [uvm_test_top] Reset now inactive
218: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 30411113: uvm_test_top [uvm_test_top] Reset now active
219: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 30413097: uvm_test_top [uvm_test_top] Reset now inactive
220: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 31260649: uvm_test_top [uvm_test_top] Reset now active
221: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 31262637: uvm_test_top [uvm_test_top] Reset now inactive
[E] 222: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 35002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
223:
224: --- RISC-V UVM TEST FAILED ---
225:
226: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 35002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pc_intg_test.27389
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.27389/trace_core_00000000.log not found
riscv_pc_intg_test.27392
------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.27392/trace_core_00000000.log not found
riscv_pmp_basic_test.27417
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
101: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
102: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
105: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_basic_test.27417/trace_core_00000000.log
[E] 106: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002026: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
107:
108: --- RISC-V UVM TEST FAILED ---
109:
110: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002026: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27383
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27383/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002019: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002019: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27400
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27400/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27405
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27405/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27410
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27410/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002015: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002015: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27419
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27419/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.27426
----------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.27426/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002025: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002025: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.27381
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
125: 977376: Illegal instruction (hart 0) at PC 0x800035ba: 0x3a0a6073
126: 977396: Illegal instruction (hart 0) at PC 0x800035ba: 0x3a0a6073
127: 977416: Illegal instruction (hart 0) at PC 0x800035ba: 0x3a0a6073
128: 1016116: Illegal instruction (hart 0) at PC 0x800035cc: 0x3b0c1073
129: 1016156: Illegal instruction (hart 0) at PC 0x800035cc: 0x3b0c1073
[E] 130: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1032286: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 800035d6
131:
132:
133: --- RISC-V UVM TEST FAILED ---
134:
--------------------------------------------
riscv_pmp_full_random_test.27398
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2033: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2033: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2033: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2033: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27398/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 76353: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 18000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27413
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27413/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1855626: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 31384000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27414
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2023: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2023: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2023: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2023: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27414/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 41843: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 1499000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27427
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
135: 111372: Illegal instruction (hart 0) at PC 0x800033a0: 0x3a096073
136: 111392: Illegal instruction (hart 0) at PC 0x800033a0: 0x3a096073
137: 111392: Illegal instruction (hart 0) at PC 0x800033a0: 0x3a096073
138: 111412: Illegal instruction (hart 0) at PC 0x800033a0: 0x3a096073
139: 111432: Illegal instruction (hart 0) at PC 0x800033a0: 0x3a096073
[E] 140: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 111662: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 42a99780 but store at address 80035ce0 was expected
141: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
142:
143:
144: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27432
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2040: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2040: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2040: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2040: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27432/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 56200: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 9390000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27445
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27445/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 356779: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 48f18000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27454
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27454/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 76464: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80004508
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27456
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2011: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2011: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2011: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27456/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 37571: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 7f800000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27457
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27457/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 668668: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80005a2c
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27464
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27464/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 539360: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80006ce8
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27489
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27489/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1919508: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 79800000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27490
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27490/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1456018: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 3e000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27500
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27500/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 562394: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 692c2000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27503
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
149: 1395494: Illegal instruction (hart 0) at PC 0x80003494: 0x7470d073
150: 1395514: Illegal instruction (hart 0) at PC 0x80003494: 0x7470d073
151: 1395514: Illegal instruction (hart 0) at PC 0x80003494: 0x7470d073
152: 1395534: Illegal instruction (hart 0) at PC 0x80003494: 0x7470d073
153: 1395554: Illegal instruction (hart 0) at PC 0x80003494: 0x7470d073
[E] 154: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1396024: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80035ce0 was expected
155: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
156:
157:
158: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27504
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2021: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2021: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2021: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27504/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1959981: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 25c00000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27508
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27508/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 178062: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 747b000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27518
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27518/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 35478: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 1e000000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002200 but the DUT didn't report one at PC 80002282
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27540
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27540/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 32415: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 60000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27548
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
127: 750454: Illegal instruction (hart 0) at PC 0x800033b2: 0x3b079073
128: 2425954: Illegal instruction (hart 0) at PC 0x80003564: 0x3a0b6073
129: 2425974: Illegal instruction (hart 0) at PC 0x80003564: 0x3a0b6073
130: 2425994: Illegal instruction (hart 0) at PC 0x80003564: 0x3a0b6073
131: 2426014: Illegal instruction (hart 0) at PC 0x80003564: 0x3a0b6073
[E] 132: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2426244: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 275c4000 but store at address 80035ce0 was expected
133: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
134:
135:
136: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27557
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27557/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1567222: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 10000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27574
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27574/trace_core_00000000.log
112: 23439: Illegal instruction (hart 0) at PC 0x800032b0: 0x3a0ae073
113: 23459: Illegal instruction (hart 0) at PC 0x800032b0: 0x3a0ae073
114: 23479: Illegal instruction (hart 0) at PC 0x800032b0: 0x3a0ae073
115: 23499: Illegal instruction (hart 0) at PC 0x800032b0: 0x3a0ae073
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 25169: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address bbf5c00 but store at address 80035ce0 was expected
117: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
118:
119:
120: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27584
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27584/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 576405: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 1dc40000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27587
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27587/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 128008: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 80000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27596
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27596/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1156607: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 50000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27603
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2019: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2019: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2019: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27603/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 116799: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 6f212500 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27616
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: 68108: Illegal instruction (hart 0) at PC 0x800195ac: 0x3b091073
118: 82808: Illegal instruction (hart 0) at PC 0x800195b0: 0x3a086073
119: 82848: Illegal instruction (hart 0) at PC 0x800195b0: 0x3a086073
120: 104368: Illegal instruction (hart 0) at PC 0x800195c2: 0x3b091073
121: 104408: Illegal instruction (hart 0) at PC 0x800195c2: 0x3b091073
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1201898: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 5f513b80 but store at address 80036ce0 was expected
123: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
124:
125:
126: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27627
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
117: 417660: Illegal instruction (hart 0) at PC 0x80003308: 0x3a08e073
118: 454760: Illegal instruction (hart 0) at PC 0x80003308: 0x3a08e073
119: 454800: Illegal instruction (hart 0) at PC 0x80003308: 0x3a08e073
120: 470700: Illegal instruction (hart 0) at PC 0x8000331a: 0x3b0f1073
121: 470740: Illegal instruction (hart 0) at PC 0x8000331a: 0x3b0f1073
[E] 122: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 504410: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80003324
123:
124:
125: --- RISC-V UVM TEST FAILED ---
126:
--------------------------------------------
riscv_pmp_full_random_test.27645
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27645/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 713347: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000354a
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27650
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27650/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 808605: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 40000000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27657
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27657/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2882996: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 6b000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27667
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2012: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2012: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2012: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27667/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 894712: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27689
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27689/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 122209: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 70000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27695
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
131: 2467474: Illegal instruction (hart 0) at PC 0x8001aff2: 0x3b0f1073
132: 2492314: Illegal instruction (hart 0) at PC 0x8001aff6: 0x3a09e073
133: 2492354: Illegal instruction (hart 0) at PC 0x8001aff6: 0x3a09e073
134: 2506614: Illegal instruction (hart 0) at PC 0x8001b008: 0x3b0f1073
135: 2506654: Illegal instruction (hart 0) at PC 0x8001b008: 0x3b0f1073
[E] 136: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2950924: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 59800000 but store at address 80036ce0 was expected
137: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
138:
139:
140: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27699
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27699/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 101145: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 7e1e2000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27718
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27718/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 153906: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 80000000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27719
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2016: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2016: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27719/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2301176: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80004132
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27741
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27741/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 31720: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 1f3e2000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 80002482
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27744
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27744/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 334524: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 97aeb00 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27748
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27748/trace_core_00000000.log
112: 34442: Illegal instruction (hart 0) at PC 0x80003be6: 0x3a0be073
113: 34482: Illegal instruction (hart 0) at PC 0x80003be6: 0x3a0be073
114: 92742: Illegal instruction (hart 0) at PC 0x80003bf8: 0x3b0e9073
115: 92782: Illegal instruction (hart 0) at PC 0x80003bf8: 0x3b0e9073
[E] 116: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1867492: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 8abe400 but store at address 80036ce0 was expected
117: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
118:
119:
120: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27755
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: 407667: Illegal instruction (hart 0) at PC 0x800032c6: 0x3a086073
114: 448667: Illegal instruction (hart 0) at PC 0x800032c6: 0x3a086073
115: 448707: Illegal instruction (hart 0) at PC 0x800032c6: 0x3a086073
116: 466427: Illegal instruction (hart 0) at PC 0x800032d8: 0x3b029073
117: 466467: Illegal instruction (hart 0) at PC 0x800032d8: 0x3b029073
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 974777: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 66324580 but store at address 80035ce0 was expected
119: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
120:
121:
122: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27756
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27756/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 51414: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 5f281410 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27762
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2048: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2048: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2048: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2048: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27762/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 24088: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 1c800000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27776
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2024: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2024: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27776/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 457884: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 35d30000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27784
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2026: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2026: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2026: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27784/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 413226: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 45990000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27791
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27791/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 42557: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 29084000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27796
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27796/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2484335: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 49cda000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27812
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2025: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2025: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2025: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27812/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 187965: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 11045000 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27813
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: 959932: Illegal instruction (hart 0) at PC 0x8000363e: 0x3a0a6073
114: 997992: Illegal instruction (hart 0) at PC 0x8000363e: 0x3a0a6073
115: 998032: Illegal instruction (hart 0) at PC 0x8000363e: 0x3a0a6073
116: 1026292: Illegal instruction (hart 0) at PC 0x8000364e: 0x3b049073
117: 1026332: Illegal instruction (hart 0) at PC 0x8000364e: 0x3b049073
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1042042: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 760de800 but store at address 80035ce0 was expected
119: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
120:
121:
122: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27819
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2030: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2030: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2030: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2030: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27819/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 480010: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 2b266280 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27837
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2014: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2014: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2014: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27837/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 154194: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80003e8c
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27841
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2015: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2015: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2015: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27841/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1723515: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 0 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27864
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2029: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27864/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 83809: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 40000000 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 80002582
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27869
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27869/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 232147: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 8000429a
113:
114:
115: --- RISC-V UVM TEST FAILED ---
116:
--------------------------------------------
riscv_pmp_full_random_test.27889
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
137: 2112308: Illegal instruction (hart 0) at PC 0x80003708: 0x3a0a6073
138: 2112328: Illegal instruction (hart 0) at PC 0x80003708: 0x3a0a6073
139: 2112328: Illegal instruction (hart 0) at PC 0x80003708: 0x3a0a6073
140: 2112348: Illegal instruction (hart 0) at PC 0x80003708: 0x3a0a6073
141: 2112368: Illegal instruction (hart 0) at PC 0x80003708: 0x3a0a6073
[E] 142: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2112598: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 78505000 but store at address 80035ce0 was expected
143: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
144:
145:
146: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27892
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27892/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 547228: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 385a4200 but store at address 80036ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002600 but the DUT didn't report one at PC 80002682
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27915
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
529: 3532413: Illegal instruction (hart 0) at PC 0x80006fa4: 0x3b071073
530: 3659553: Illegal instruction (hart 0) at PC 0x80007230: 0x3a086073
531: 3659593: Illegal instruction (hart 0) at PC 0x80007230: 0x3a086073
532: 3677953: Illegal instruction (hart 0) at PC 0x80007240: 0x3b071073
533: 3677993: Illegal instruction (hart 0) at PC 0x80007240: 0x3b071073
[E] 534: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 3701543: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 7840000 but store at address 80035ce0 was expected
535: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
536:
537:
538: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.27950
--------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2027: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2027: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2027: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.27950/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 34787: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated store at address 52f26500 but store at address 80035ce0 was expected
113: Synchronous trap was expected at ISS PC: 80002700 but the DUT didn't report one at PC 80002782
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_epmp_mmwp_test.27388
--------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
103: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
104: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_epmp_mmwp_test.27388/trace_core_00000000.log
[E] 108: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
109:
110: --- RISC-V UVM TEST FAILED ---
111:
112: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------