Ibex Regression Results
Date/Time run: Thursday 04 July 2024 04:06 UTC
| Test Name | Passing | Total | Pass Rate |
|---|
| riscv_arithmetic_basic_test |
10 |
10 |
100.0% |
| riscv_machine_mode_rand_test |
10 |
10 |
100.0% |
| riscv_rand_instr_test |
10 |
10 |
100.0% |
| riscv_rand_jump_test |
10 |
10 |
100.0% |
| riscv_jump_stress_test |
10 |
10 |
100.0% |
| riscv_loop_test |
10 |
10 |
100.0% |
| riscv_mmu_stress_test |
10 |
10 |
100.0% |
| riscv_illegal_instr_test |
15 |
15 |
100.0% |
| riscv_hint_instr_test |
10 |
10 |
100.0% |
| riscv_ebreak_test |
10 |
10 |
100.0% |
| riscv_debug_basic_test |
9 |
10 |
90.0% |
| riscv_debug_triggers_test |
5 |
5 |
100.0% |
| riscv_debug_stress_test |
15 |
15 |
100.0% |
| riscv_debug_branch_jump_test |
9 |
10 |
90.0% |
| riscv_debug_instr_test |
25 |
25 |
100.0% |
| riscv_debug_wfi_test |
10 |
10 |
100.0% |
| riscv_dret_test |
3 |
5 |
60.0% |
| riscv_debug_ebreak_test |
15 |
15 |
100.0% |
| riscv_debug_ebreakmu_test |
15 |
15 |
100.0% |
| riscv_debug_csr_entry_test |
10 |
10 |
100.0% |
| riscv_irq_in_debug_mode_test |
10 |
10 |
100.0% |
| riscv_debug_in_irq_test |
10 |
10 |
100.0% |
| riscv_assorted_traps_interrupts_debug_test |
4 |
10 |
40.0% |
| riscv_single_interrupt_test |
15 |
15 |
100.0% |
| riscv_multiple_interrupt_test |
10 |
10 |
100.0% |
| riscv_nested_interrupt_test |
10 |
10 |
100.0% |
| riscv_interrupt_instr_test |
25 |
25 |
100.0% |
| riscv_interrupt_wfi_test |
15 |
15 |
100.0% |
| riscv_interrupt_csr_test |
10 |
10 |
100.0% |
| riscv_csr_test |
5 |
5 |
100.0% |
| riscv_unaligned_load_store_test |
5 |
5 |
100.0% |
| riscv_mem_error_test |
15 |
15 |
100.0% |
| riscv_mem_intg_error_test |
46 |
50 |
92.0% |
| riscv_debug_single_step_test |
13 |
15 |
86.7% |
| riscv_reset_test |
14 |
15 |
93.3% |
| riscv_pc_intg_test |
12 |
15 |
80.0% |
| riscv_rf_intg_test |
15 |
15 |
100.0% |
| riscv_rf_ctrl_intg_test |
15 |
15 |
100.0% |
| riscv_icache_intg_test |
15 |
15 |
100.0% |
| riscv_rv32im_instr_test |
5 |
5 |
100.0% |
| riscv_user_mode_rand_test |
10 |
10 |
100.0% |
| riscv_umode_tw_test |
10 |
10 |
100.0% |
| riscv_invalid_csr_test |
10 |
10 |
100.0% |
| riscv_pmp_basic_test |
50 |
50 |
100.0% |
| riscv_pmp_disable_all_regions_test |
50 |
50 |
100.0% |
| riscv_pmp_out_of_bounds_test |
45 |
50 |
90.0% |
| riscv_pmp_full_random_test |
598 |
600 |
99.7% |
| riscv_pmp_region_exec_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_execute_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mml_read_only_test |
20 |
20 |
100.0% |
| riscv_epmp_mmwp_test |
20 |
20 |
100.0% |
| riscv_epmp_rlb_test |
20 |
20 |
100.0% |
| riscv_bitmanip_otearlgrey_test |
10 |
10 |
100.0% |
| riscv_bitmanip_balanced_test |
10 |
10 |
100.0% |
| Total |
1403 |
1430 |
98.1% |
Coverage
| Functional | Block | Branch | Statement | Expression | Toggle | FSM | Assertion |
|---|
| 94.0% |
95.9% |
90.6% |
95.9% |
90.7% |
97.2% |
100.0% |
98.1% |
Test Failure Details
riscv_debug_basic_test.3683
---------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
393: 14537786: Illegal instruction (hart 0) at PC 0x80000444: 0x34202ff3
394: 14537806: Illegal instruction (hart 0) at PC 0x80000444: 0x34202ff3
395: 14537826: Illegal instruction (hart 0) at PC 0x80000444: 0x34202ff3
396: 14621206: Illegal instruction (hart 0) at PC 0x80000444: 0x34202ff3
397: 14621246: Illegal instruction (hart 0) at PC 0x80000444: 0x34202ff3
[E] 398: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(904) @ 14698696: uvm_test_top [uvm_test_top] No dret detected, or incorrect privilege mode switch in timeout period of 100000 cycles
399:
400: --- RISC-V UVM TEST FAILED ---
401:
402: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 14698696: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_branch_jump_test.3681
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2029: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_debug_branch_jump_test.3681/trace_core_00000000.log
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv(43) @ 26109: reporter@@debug_seq_stress_h [debug_seq_stress_h] Starting sequence...
[E] 113: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 36002029: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
114:
115: --- RISC-V UVM TEST FAILED ---
116:
117: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 36002029: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.3678
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.3678/trace_core_00000000.log
108: 48748: Illegal instruction (hart 0) at PC 0x80003720: 0x7b200073
109: 48788: Illegal instruction (hart 0) at PC 0x80003720: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(850) @ 65458: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(915) @ 72478: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 72478: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_dret_test.3681
--------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2029: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
107: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_dret_test.3681/trace_core_00000000.log
108: 147279: Illegal instruction (hart 0) at PC 0x80010fe0: 0x7b200073
109: 147319: Illegal instruction (hart 0) at PC 0x80010fe0: 0x7b200073
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(850) @ 166309: uvm_test_top [uvm_test_top] mcause: 0x2
[E] 111: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(915) @ 171389: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
112:
113: --- RISC-V UVM TEST FAILED ---
114:
115: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 171389: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3678
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
2097: 33023088: Illegal instruction (hart 0) at PC 0xa22107b8: 0x00010413
2098: 33023128: Illegal instruction (hart 0) at PC 0xa22107b8: 0x00010413
2099: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
2100: IRQs last cycle: 02000, IRQs this cycle: 00000
2101: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 33084998 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 2102: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 33084998: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
2103:
2104: --- RISC-V UVM TEST FAILED ---
2105:
2106: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 33084998: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3680
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
2522: 31167702: Illegal instruction (hart 0) at PC 0x00001248: 0x00010413
2523: 31167742: Illegal instruction (hart 0) at PC 0x00001248: 0x00010413
2524: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
2525: IRQs last cycle: 00100, IRQs this cycle: 00000
2526: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 31188392 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 2527: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 31188392: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
2528:
2529: --- RISC-V UVM TEST FAILED ---
2530:
2531: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 31188392: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3681
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
594: 8741659: Illegal instruction (hart 0) at PC 0x0c2c82b8: 0x00010413
595: 8741699: Illegal instruction (hart 0) at PC 0x0c2c82b8: 0x00010413
596: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
597: IRQs last cycle: 00008, IRQs this cycle: 00000
598: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 8774469 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 599: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 8774469: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
600:
601: --- RISC-V UVM TEST FAILED ---
602:
603: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 8774469: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3682
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
2095: 38918309: Illegal instruction (hart 0) at PC 0x00000ae4: 0x00010413
2096: 38948869: Illegal instruction (hart 0) at PC 0x00000ae8: 0x00010413
2097: 38948909: Illegal instruction (hart 0) at PC 0x00000ae8: 0x00010413
2098: 38984209: Illegal instruction (hart 0) at PC 0x00000aec: 0x00010413
2099: 38984249: Illegal instruction (hart 0) at PC 0x00000aec: 0x00010413
[E] 2100: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 39002019: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
2101:
2102: --- RISC-V UVM TEST FAILED ---
2103:
2104: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 39002019: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3683
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
560: 9170286: Illegal instruction (hart 0) at PC 0xde21e36e: 0x00010413
561: 9170326: Illegal instruction (hart 0) at PC 0xde21e36e: 0x00010413
562: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
563: IRQs last cycle: 04000, IRQs this cycle: 00000
564: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 9195876 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 565: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 9195876: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
566:
567: --- RISC-V UVM TEST FAILED ---
568:
569: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 9195876: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_assorted_traps_interrupts_debug_test.3685
-----------------------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
2201: 23686900: Illegal instruction (hart 0) at PC 0x00000f30: 0x00010413
2202: 23686940: Illegal instruction (hart 0) at PC 0x00000f30: 0x00010413
2203: WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE
2204: IRQs last cycle: 01000, IRQs this cycle: 00000
2205: xmsim: *E,ASRTST (/home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv,995): (time 23714650 NS) Assertion core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.IbexSetExceptionPCOnSpecialReqIfExpected has failed
[E] 2206: UVM_ERROR /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/rtl/ibex_controller.sv(995) @ 23714650: reporter [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
2207:
2208: --- RISC-V UVM TEST FAILED ---
2209:
2210: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 23714650: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_mem_intg_error_test.3682
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1715) @ 13459: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13459: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 49479: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 68359: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
118: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 89519: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 119: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 127779: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x2 DUT: 80012ee6 expected: 0
120:
121:
122: --- RISC-V UVM TEST FAILED ---
123:
--------------------------------------------
riscv_mem_intg_error_test.3683
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2016: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3683/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1715) @ 13996: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 13996: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 13996: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 68696: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x31 DUT: 80017f7e expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.3708
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
112: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2024: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3708/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1715) @ 15544: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 15544: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 15544: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 117: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 57064: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x31 DUT: 8001365f expected: 0
118:
119:
120: --- RISC-V UVM TEST FAILED ---
121:
--------------------------------------------
riscv_mem_intg_error_test.3725
------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
113: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_mem_intg_error_test.3725/trace_core_00000000.log
114: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv(1715) @ 12391: uvm_test_top [uvm_test_top] Running core_ibex_mem_error_test
115: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 12391: uvm_test_top.env.vseqr@@memory_error_seq_h [uvm_test_top.env.vseqr.memory_error_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
116: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 12391: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
117: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv(165) @ 110771: reporter [core_ibex_tb_top.unmblk1] Disabling assertions: core_ibex_tb_top.NoAlertsTriggered
[E] 118: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 141371: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch Register write data mismatch to x8 DUT: 8001ae24 expected: 0
119:
120:
121: --- RISC-V UVM TEST FAILED ---
122:
--------------------------------------------
riscv_debug_single_step_test.3678
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
15757: 38999768: Illegal instruction (hart 0) at PC 0x8000bf2a: 0xf9f47ffc
15758: 39000568: Illegal instruction (hart 0) at PC 0x8000bf2a: 0xf9f47ffc
15759: 39000608: Illegal instruction (hart 0) at PC 0x8000bf2a: 0xf9f47ffc
15760: 39001728: Illegal instruction (hart 0) at PC 0x8000bf2a: 0xf9f47ffc
15761: 39001768: Illegal instruction (hart 0) at PC 0x8000bf2a: 0xf9f47ffc
[E] 15762: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 39002018: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
15763:
15764: --- RISC-V UVM TEST FAILED ---
15765:
15766: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 39002018: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_debug_single_step_test.3680
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
215: 1243482: Illegal instruction (hart 0) at PC 0x40000112: 0x00010413
216: 1255002: Illegal instruction (hart 0) at PC 0x40000116: 0x00010413
217: 1255042: Illegal instruction (hart 0) at PC 0x40000116: 0x00010413
218: 1295582: Illegal instruction (hart 0) at PC 0x4000011a: 0x00010413
219: 1295622: Illegal instruction (hart 0) at PC 0x4000011a: 0x00010413
[E] 220: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 1295652: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT didn't write to register x1, but a write was expected
221:
222:
223: --- RISC-V UVM TEST FAILED ---
224:
--------------------------------------------
riscv_reset_test.3680
---------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [1800s].
---------------*LOG-EXTRACT*----------------
211: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 26623872: uvm_test_top [uvm_test_top] Reset now inactive
212: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 26684752: uvm_test_top [uvm_test_top] Reset now active
213: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 26686732: uvm_test_top [uvm_test_top] Reset now inactive
214: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(253) @ 26857970: uvm_test_top [uvm_test_top] Reset now active
215: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(260) @ 26859952: uvm_test_top [uvm_test_top] Reset now inactive
[E] 216: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 33002012: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [1800s]
217:
218: --- RISC-V UVM TEST FAILED ---
219:
220: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 33002012: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pc_intg_test.3678
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3678/trace_core_00000000.log not found
riscv_pc_intg_test.3684
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3684/trace_core_00000000.log not found
riscv_pc_intg_test.3687
-----------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: Processing the ibex trace failed: Logfile /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pc_intg_test.3687/trace_core_00000000.log not found
riscv_pmp_out_of_bounds_test.3689
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2010: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3689/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3694
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2028: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2028: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2028: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3694/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002028: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002028: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3718
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2020: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2020: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2020: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3718/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002020: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002020: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3721
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2010: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2010: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2010: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3721/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002010: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002010: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_out_of_bounds_test.3723
---------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILURE] Simulation ended gracefully due to timeout [300s].
---------------*LOG-EXTRACT*----------------
105: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2017: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 300s
106: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2017: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2017: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
109: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_out_of_bounds_test.3723/trace_core_00000000.log
[E] 110: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(326) @ 6002017: uvm_test_top [uvm_test_top] Test failed due to wall-clock timeout. [300s]
111:
112: --- RISC-V UVM TEST FAILED ---
113:
114: UVM_INFO /nas/lowrisc/tools/cadence/xcelium/21.09-s006/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_catcher.svh(705) @ 6002017: reporter [UVM/REPORT/CATCHER]
--------------------------------------------
riscv_pmp_full_random_test.3696
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2022: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2022: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2022: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.3696/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 405202: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 55bd8000 with data 80 but data aa was expected with byte mask 1
113: Synchronous trap was expected at ISS PC: 80002400 but the DUT didn't report one at PC 800042b6
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------
riscv_pmp_full_random_test.4113
-------------------------------
binary: test.bin
rtl_log: rtl_sim.log
rtl_trace: trace_core_00000000.log
iss_cosim_trace: spike_cosim_trace_core_00000000.log
[FAILED]: error seen in 'rtl_sim.log'
---------------*LOG-EXTRACT*----------------
107: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv(315) @ 2018: uvm_test_top [uvm_test_top] Test wall-clock timeout is set to : 180s
108: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.instr_if_response_agent.sequencer@@instr_intf_seq [uvm_test_top.env.instr_if_response_agent.sequencer.instr_intf_seq] is_dmem_seq: 0x0
109: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv(35) @ 2018: uvm_test_top.env.data_if_response_agent.sequencer@@data_intf_seq [uvm_test_top.env.data_if_response_agent.sequencer.data_intf_seq] is_dmem_seq: 0x1
110: UVM_INFO /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv(65) @ 2018: reporter@@fetch_enable_seq_h [fetch_enable_seq_h] Running the "InfiniteRuns" schedule for stimulus generation
111: core_ibex_tb_top.dut.u_ibex_tracer.unmblk2.unmblk1: Writing execution trace to /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/out/run/tests/riscv_pmp_full_random_test.4113/trace_core_00000000.log
[E] 112: UVM_FATAL /home/runner/_work/lowrisc-private-ci/lowrisc-private-ci/ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv(168) @ 2969578: uvm_test_top.env.cosim_agent.scoreboard [uvm_test_top.env.cosim_agent.scoreboard] Cosim mismatch DUT generated load at address 40000000 with data 0 but data 18 was expected with byte mask 1
113: Synchronous trap was expected at ISS PC: 80002500 but the DUT didn't report one at PC 8000e052
114:
115:
116: --- RISC-V UVM TEST FAILED ---
--------------------------------------------